GaN Gate Regulator Circuit for MOSFET-Compatible Voltage Clamping
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Solution Overview
Problem
Gallium nitride (GaN) field effect transistors (FETs) are prone to false activation and damage due to their narrow gate driving voltage range (−3 V to +7 V), which is different from silicon MOSFETs and silicon carbide MOSFETs, posing integration challenges and robustness issues.
Innovation Solution
A circuit design that regulates the input control voltage range for GaN FETs to match that of MOSFETs, increasing the gate threshold voltage and expanding the driving range, while maintaining fast switching capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If GaN FET is used with standard MOSFET gate driving voltage range (−20 V to +20 V), then compatibility with existing MOSFET systems is improved, but GaN FET may be damaged due to exceeding its narrow gate driving voltage range (−3 V to +7 V)
Solution Approach 1:
A gate regulator circuit is introduced as an intermediary component between the MOSFET gate driver and the GaN FET gate terminal. This regulator circuit receives the standard MOSFET gate driving voltage (−20 V to +20 V) and transforms it into the appropriate GaN FET gate voltage range (−3 V to +7 V), enabling compatibility while protecting the GaN FET from damage
Solution Approach 2:
The gate regulator circuit dynamically adjusts the gate voltage parameters by clamping the maximum voltage to +7 V and the minimum voltage to −3 V, regardless of the input voltage level. This parameter transformation allows the GaN FET to operate safely within its narrow voltage range while maintaining compatibility with standard MOSFET driving circuits
2Ease of operation
If GaN FET operates with low threshold voltage (1 V to 2 V), then easier turn-on is achieved, but false turn-on due to noise increases
Solution Approach 1:
The gate regulator circuit modifies the gate voltage parameters by implementing voltage clamping that raises the effective threshold voltage. By clamping the gate voltage to a maximum of +7 V and minimum of −3 V, the circuit creates a higher noise margin that prevents false turn-on while maintaining ease of operation through the regulated voltage swing
3Reliability
If gate threshold voltage is increased to match MOSFET levels, then robustness and noise immunity are improved, but switching speed may be reduced
Solution Approach 1:
The gate regulator circuit employs dynamic voltage regulation that adapts the gate voltage characteristics based on the switching state. During switching transitions, the circuit provides adequate voltage swing to maintain fast switching speed, while during steady-state operation, the clamping effect establishes a higher effective threshold voltage for improved robustness and noise immunity
Solution Approach 2:
The gate regulator operates in a periodic manner during switching cycles, rapidly adjusting the gate voltage to maintain the optimal balance between threshold voltage and switching speed. This periodic regulation ensures that the GaN FET achieves both robustness and fast switching performance
Data Source
AI summary
An integrated circuit includes a main switch, wherein the main switch comprises a first high electron mobility transistor (HEMT). The integrated circuit includes a subcircuit comprising a plurality of second HEMTs, a gate of the main switch is electrically connected to the subcircuit, each of the plurality of second HEMTs is drain-to-gate connected. The integrated circuit includes a third HEMT electrically connected to the gate of the main switch, wherein the third HEMT is drain-to-gate connected, and a drain of the third HEMT is electrically connected to a source of the main switch. The integrated circuit includes a fourth HEMT electrically connected to the gate of the main switch, the fourth HEMT is drain-to-gate connected. The integrated circuit includes a fifth HEMT electrically connected to the gate of the main switch, wherein the fifth HEMT is source-to-gate connected, and the fourth HEMT is connected in parallel with the fifth HEMT.