GaN Transistor Gate Circuit for Slew Rate and EMI Control
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Solution Overview
Problem
III-V semiconductor transistors, such as GaN-based HEMTs and MISHEMTs, exhibit fast switching rates that lead to ringing and higher order harmonics, resulting in electromagnetic interference, which requires expensive filtering components to mitigate.
Innovation Solution
The implementation of control circuits that include a first transistor, a capacitor, and a second transistor to control the slew rate of III-V semiconductor transistors during switching, employing pulse-width modulation signals and impedance insertion to slow down voltage rise, thereby minimizing electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fast switching rates are used in III-V semiconductor transistors, then switching speed is improved, but electromagnetic interference increases
Solution Approach 1:
The patent introduces an intermediary circuit between the control signal source and the III-V semiconductor transistor gate. This circuit includes a first transistor, capacitor, and second transistor that work together to control the slew rate of the gate voltage, thereby mediating between the fast switching capability of the device and the electromagnetic interference problem
Solution Approach 2:
The patent dynamically changes the slew rate parameter of the gate voltage by controlling the charging and discharging of the capacitor through the transistor switches. By adjusting the voltage rise time (dV/dt) as a controllable parameter, the circuit maintains fast switching when needed while reducing electromagnetic interference when appropriate
2Object-generated harmful factors
If expensive filtering components are added to minimize electromagnetic interference, then electromagnetic interference is reduced, but device complexity and cost increase
Solution Approach 1:
The patent converts the inherently fast switching characteristic that causes electromagnetic interference into a beneficial feature by controlling its rate of change. The same fast switching capability is preserved while the slew rate is managed through the transistor-capacitor circuit, turning a harmful effect into a controllable parameter without requiring external filtering components
3Object-generated harmful factors
If slew rate control circuit is added to minimize electromagnetic interference, then electromagnetic interference is reduced, but device complexity increases
Solution Approach 1:
The patent merges the slew rate control function with the existing transistor switching circuitry. The first transistor, capacitor, and second transistor are integrated into the gate control path, combining the switching function and slew rate control in a single unified circuit rather than adding a separate control stage
Solution Approach 2:
The transistor-capacitor circuit serves multiple functions: it acts as a switch control element, a slew rate limiter, and a timing element all in one configuration. The same components that control the switching also control the voltage rise time, providing multi-functionality without additional complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the need for expensive filtering components by stabilizing the slew rate and minimizing electromagnetic interference, enhancing the performance of III-V semiconductor transistors in RF and mmWave applications.
Implementation Method 1
The capacitor can have a first plate connected to the first drain region and a second plate opposite the first plate
Data Source
AI summary
Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.