GaN Gate Structure for Unified D-Mode and E-Mode Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of D-mode and E-mode GaN devices in the same semiconductor process is challenging due to differences in etching selectivity, leading to layer structure damage and electrical performance issues during the photolithography process.
Innovation Solution
A novel semiconductor process is developed, featuring specific device passivation layers and etching steps that prevent layer damage by using Al-based and Si-based passivation layers, and a combined photolithography process with wet etching to form gate contact openings, ensuring flat surfaces and reducing over-etching effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single photolithography process is used for both D-mode and E-mode GaN devices, then manufacturing complexity is reduced, but layer structure damage occurs due to over-etching
Solution Approach 1:
An Al-based passivation layer is introduced as an intermediary protective layer between the etching process and the underlying layer structures. This passivation layer has different etching selectivity compared to the Si-based passivation layer, allowing the etching process to selectively remove the Si-based layer without damaging the underlying GaN layers or p-GaN layer, thus preventing over-etching damage while maintaining a unified photolithography process
Solution Approach 2:
Different passivation layers (Al-based and Si-based) are applied to different regions or depths of the structure to provide localized protection. The Al-based passivation layer specifically protects regions that are more susceptible to over-etching, while the Si-based passivation layer provides general protection, creating a multi-layered defense strategy that maintains layer structure integrity during the etching process
2Manufacturing precision
If separate photolithography processes are used for D-mode and E-mode GaN devices, then layer structure integrity is maintained, but manufacturing complexity and production time increase
Solution Approach 1:
The patent merges the photolithography processes for D-mode and E-mode GaN devices into a single unified process. By using multiple passivation layers with different etching selectivities, the process can simultaneously handle both device types without requiring separate etching steps, thus maintaining layer structure integrity while improving production efficiency and reducing manufacturing complexity
3Reliability
If additional p-GaN layer is added for E-mode devices, then normally-off characteristic is achieved, but etching selectivity differences cause layer damage
Solution Approach 1:
The Al-based passivation layer is deposited beforehand as a cushioning protective layer specifically to prevent etching damage to the p-GaN layer and underlying structures. This passivation layer acts as a buffer that absorbs the aggressive etching effects, ensuring that the p-GaN layer maintains its integrity and electrical performance characteristics during the photolithography process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the simultaneous manufacturing of D-mode and E-mode GaN devices with improved electrical performance by preventing layer damage and simplifying the production process, reducing production costs and cycle time.
Implementation Method 1
The layer structures of GaN devices of different modes will have quite different etching selectivity in the same etching process
Implementation Method 2
performing a photolithography process to form gate contact openings simultaneously in the first region and the second region, wherein one of the gate contact openings on the first region extends through the Si-based passivation layer and the Al-based passivation layer
Data Source
AI summary
A semiconductor device provided with features of depletion mode (D-mode) and enhancement mode (E-mode) GaN devices, including a substrate with a first region and a second region defined thereon, a GaN channel layer on the substrate, a AlGaN layer on the GaN channel layer, a p-GaN layer on the AlGaN layer in the first region, a Al-based passivation layer on the AlGaN layer and p-GaN layer, and gate contact openings, wherein the gate contact opening on the first region extends through the Al-based passivation layer to the top surface of p-GaN layer, the gate contact opening on the second region extends through the Al-based passivation layer to the surface of AlGaN layer, and the surfaces of p-GaN layer and AlGaN layer are both flat surfaces without recess feature.