GaN Laminated Structure on Glass for Low-Temperature Crystallinity

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Solution Overview

Problem

The use of expensive sapphire or quartz glass substrates for gallium nitride-based semiconductor layers hinders the increase in display screen area and decreases throughput due to high processing temperatures, which are typically above 1000°C.

Innovation Solution

A laminated structure is formed using a highly crystalline gallium nitride-based semiconductor layer on an inexpensive amorphous substrate, such as a glass substrate, with a base layer and orientation layer to improve crystallinity and reduce processing temperature, allowing for large-area manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If expensive sapphire or quartz glass substrates are used for gallium nitride-based semiconductor layers, then high crystallinity and device performance are achieved, but manufacturing cost increases and substrate area is limited

Engineering Contradiction:
ImprovecrystallinityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent replaces expensive sapphire or quartz glass substrates with inexpensive amorphous substrates (such as glass substrates) that can be processed at lower temperatures. The amorphous substrate serves as a cost-effective base for forming the gallium nitride semiconductor layer, eliminating the need for costly crystalline substrates while maintaining device performance through proper layer structure design

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the processing temperature parameter from high temperatures (above 1000°C) required for sapphire substrates to lower temperatures (800°C or below) suitable for amorphous substrates. This parameter change enables the use of inexpensive amorphous materials while still achieving high crystallinity in the gallium nitride layer through controlled deposition processes

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If high processing temperatures above 1000°C are used for gallium nitride layer formation, then high crystallinity is achieved, but throughput decreases and manufacturing efficiency is reduced

Engineering Contradiction:
ImprovecrystallinityVSAvoidthroughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent fundamentally changes the temperature parameter from above 1000°C to 800°C or below, enabling faster processing cycles and higher throughput. The lower temperature process allows for rapid deposition and formation of the gallium nitride layer without the time-consuming high-temperature annealing required by conventional methods

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary formation of the orientation layer and buffer layer on the amorphous substrate before depositing the gallium nitride semiconductor layer. This preliminary structuring at lower temperatures prepares the substrate in advance, eliminating the need for subsequent high-temperature processing steps and enabling continuous manufacturing with high throughput

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If amorphous substrates are used instead of sapphire substrates, then manufacturing cost decreases and substrate area increases, but achieving high crystallinity becomes more difficult

Engineering Contradiction:
Improvemanufacturing costVSAvoidcrystallinity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces an orientation layer as an intermediary between the amorphous substrate and the gallium nitride semiconductor layer. This orientation layer, formed at lower temperatures, provides a crystalline template that guides the growth of highly crystalline gallium nitride on the amorphous substrate, bridging the gap between the inexpensive amorphous base and the high-performance semiconductor layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a composite structure consisting of multiple layers (amorphous substrate, buffer layer, orientation layer, and gallium nitride semiconductor layer) where each layer contributes specific properties. The combination of amorphous and crystalline materials in a controlled composite structure enables both cost-effectiveness and high crystallinity in the final device

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the production of high-definition semiconductor devices with improved productivity and throughput on a larger amorphous substrate without exposure to high temperatures, utilizing a sputtering method to form a highly crystalline semiconductor layer with specific orientation.

Implementation Method 1

utilizing a sputtering method to form a highly crystalline semiconductor layer with specific orientation

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS20250220999A1Laminated structure, method for manufacturing laminated structure, and semiconductor device
Publication Date: 2025.07.03 JAPAN DISPLAY INC
  • US20250220999A1 patent drawing
  • US20250220999A1 patent drawing
  • US20250220999A1 patent drawing

AI summary

A laminated structure includes an amorphous substrate having an insulating surface, an orientation pattern on the amorphous substrate, an insulating layer in contact with a side surface of the orientation pattern and surrounding the periphery of the orientation pattern, and a semiconductor pattern containing gallium nitride on the orientation pattern, wherein the insulating layer has a first region overlapping the semiconductor pattern and a second region not overlapping the semiconductor pattern.