GaN Half-Bridge Gate Driving to Cut Deadtime Reverse Conduction
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Solution Overview
Problem
GaN HEMT devices experience significant power losses due to reverse conduction during deadtime periods, which limit their efficiency compared to standard MOS technologies.
Innovation Solution
A half bridge adjustment circuit modifies the driver signal by introducing an intermediate voltage during the deadtime period, reducing the source-to-drain voltage and minimizing power losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If GaN HEMT devices operate with conventional square wave driver signals during deadtime, then the devices can maintain high switching speed and low on-state resistance, but significant power losses occur due to reverse conduction during deadtime periods
Solution Approach 1:
The deadtime period is segmented into two distinct phases: a first portion where both transistors remain fully off, and a second portion where the upcoming transistor is partially turned on to an intermediate state. This segmentation allows the device to reduce reverse conduction losses during the second portion while maintaining proper deadtime functionality during the first portion.
Solution Approach 2:
The driver signal transitions from a static square wave to a dynamic waveform that adapts during the deadtime period. The signal dynamically adjusts the gate voltage to an intermediate level during the second portion of deadtime, creating a time-varying control strategy that optimizes performance across different operational phases.
2Loss of energy
If an intermediate voltage is applied to the gate terminal during the second portion of deadtime, then reverse conduction losses are reduced, but the driver circuit complexity increases
Solution Approach 1:
The half bridge adjustment circuit preliminarily prepares the gate voltage during the first portion of deadtime by beginning the transition to intermediate voltage levels before the second portion begins. This preliminary action ensures that when the second portion starts, the transistor is already partially conditioned, reducing the abruptness of transitions and minimizing reverse conduction losses from the outset of the second portion.
Solution Approach 2:
The half bridge adjustment circuit acts as an intermediary component between the conventional square wave driver and the transistor gate terminal. It mediates the driver signal by inserting an intermediate voltage level during the second portion of deadtime, thereby reducing the voltage stress and power losses without requiring fundamental changes to the existing driver architecture.
3Use of energy by moving object
If the deadtime is divided into two portions with different voltage levels, then power efficiency is improved, but the control signal generation becomes more complex
Solution Approach 1:
The control signal generation employs periodic action by applying different voltage levels to the gate terminal at specific periodic intervals within each deadtime cycle. The first portion receives one voltage level (typically zero or negative), while the second portion receives an intermediate voltage level, creating a periodic modulation pattern that repeats with each switching cycle to optimize power efficiency.
Data Source
AI summary
A half bridge circuit includes two GaN high electron mobility transistors (HEMT). A driver circuit generates a high side and low side driver signals corresponding to square wave. A driver deadtime is the period between during which both driver signals are low. A half bridge adjustment circuit is coupled between the driver and the half bridge circuit and generates a modified high side driver signal and a modified low side driver signal, each including a transition from a low voltage to an intermediate voltage during the corresponding deadtime and a transition from the intermediate voltage to a high voltage at an end of the corresponding deadtime. The half bridge adjustment circuit drives the gate terminals of the high side and low side transistors with the modified high side and low side driver signals.


