Compact GaN Half-Bridge Power Switch With Low Loop Inductance

The power switch is divided into multiple independent GaN die devices, each handling a portion of the total current. This segmentation allows parallel current paths that reduce overall inductance while maintaining high power delivery capability. Each die can be optimized for low inductance independently, and the modular structure enables scalable power delivery.

The patent transitions from planar PCB-based power switches to a three-dimensional stacked architecture where GaN dies are vertically arranged and interconnected. This vertical stacking reduces the current loop area in the horizontal plane, thereby reducing inductance. The multi-layer construction allows power and ground traces to be closely coupled in adjacent layers, further minimizing loop inductance while enabling higher current handling.

The patent moves heat dissipation from a two-dimensional PCB surface to a three-dimensional vertical structure. Multiple GaN dies are stacked vertically with integrated heat sinks and thermal vias that conduct heat away from the active devices in the vertical direction. This allows the power switch to maintain a small horizontal footprint while providing adequate thermal management through vertical heat pathways.

The design nests multiple functional components within each other vertically: GaN dies are mounted on intermediate substrates that contain thermal vias, which are nested within a larger heat sink structure. This nested arrangement allows heat to be conducted from the small-area die interfaces through intermediate layers to the external heat sink, maintaining compact footprint while ensuring effective heat dissipation.

The power switch uses multiple parallel GaN die devices that can switch simultaneously. This segmentation creates multiple independent low-inductance current paths, allowing rapid switching with minimal inductance. Each die's low inductance contributes to the overall fast switching performance, and the parallel arrangement further reduces the effective inductance seen by the load.

The patent employs composite interconnect structures combining copper traces, solder layers, and ceramic or polymer substrates to create low-inductance pathways. The GaN dies themselves are composite devices with specialized metallization layers and semiconductor structures optimized for rapid switching. These composite materials and structures minimize parasitic inductance while enabling high-speed operation.