GaN HEMT Access Resistance via Low-Temp ALD Doping
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Solution Overview
Problem
High electron mobility transistors (HEMTs) made of gallium nitride-related materials face challenges in reducing parasitic capacitance and resistance around the gate electrode, which hinders high-frequency performance due to increased energy differences between the n-type GaN layer and the InAlN electron supply layer, leading to higher access resistance between the source and gate electrodes.
Innovation Solution
The HEMT design includes n-type GaN regions doped with silicon at a concentration ratio greater than 100, grown using atomic layer deposition (ALD) at temperatures below 650°C, which penetrates into the channel layer and sandwiches the InAlN barrier layer, reducing access resistance by direct contact with the channel and barrier layers, while maintaining crystal quality by suppressing carbon incorporation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type GaN regions are heavily doped with silicon to reduce access resistance, then electrical conductivity improves, but carbon incorporation increases degrading crystal quality
Solution Approach 1:
The patent applies parameter changes by precisely controlling the silicon doping concentration ratio (Si/C > 100) and growth temperature (300-650°C) during ALD processing. This resolves the contradiction by finding the optimal parameter window that achieves heavy doping for low resistance while suppressing carbon incorporation to maintain crystal quality.
Solution Approach 2:
The patent replaces conventional high-temperature MOCVD doping with low-temperature ALD doping. This substitution enables precise control of silicon incorporation at lower temperatures, achieving high doping concentrations without the carbon contamination that plagues conventional methods, thus resolving the resistance-quality tradeoff.
2Manufacturing precision
If n-type GaN regions are grown at high temperature to achieve good crystal quality, then manufacturing precision improves, but access resistance increases due to carbon incorporation
Solution Approach 1:
The patent changes the growth temperature parameter to the optimal range of 300-650°C during ALD processing. This temperature optimization simultaneously achieves good crystal quality and low carbon incorporation, while the precise silicon doping control ensures low access resistance, resolving the contradiction between quality and resistance.
Solution Approach 2:
The patent substitutes MOCVD with ALD for the doping process. This replacement enables low-temperature growth with precise dopant control, achieving both crystal quality and low resistance without the carbon incorporation problems of conventional high-temperature methods.
3Ease of manufacture
If conventional MOCVD technique is used for growing n-type GaN regions, then manufacturing ease improves, but carbon incorporation increases leading to higher access resistance
Solution Approach 1:
The patent substitutes MOCVD with ALD for the doping process. Although ALD is a more complex technique, it provides precise control over silicon incorporation and temperature, achieving low access resistance without carbon contamination. The substitution is justified by the significant improvement in electrical performance.
Solution Approach 2:
The patent changes the doping process parameters by using ALD with controlled silicon precursor supply and temperature (300-650°C). This parameter optimization achieves low access resistance without the carbon incorporation issues of MOCVD, resolving the contradiction despite the increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances trans-conductance and reduces access resistance, achieving cut-off frequencies exceeding 100 GHz and improved trans-conductance, while maintaining the crystal quality of the InAlN barrier layer by growing n-type GaN regions at lower temperatures.
Implementation Method 1
filling the recesses by growing n-type regions therein by an atomic layer deposition (ALD) technique at a temperature lower than 650° C. but higher than 300° C.
Implementation Method 2
The ALD technique may iterate steps of growing a layer containing silicon (Si) by supplying only a source for a group III element concurrently with a dopant source
Data Source
AI summary
A HEMT made of nitride semiconductor materials is disclosed. The HEMT includes the GaN channel layer, the InAlN barrier layer, and the n-type GaN regions formed beneath the source electrode and the drain electrode at a temperature such that the InAlN barrier layer in the crystal quality thereof is not degraded, lower than 800° C. The n-type GaN regions are doped with silicon (Si) and have a ratio of silicon atoms against carbon atoms (Si/C) greater than 100.