GaN HEMT Buried P-Type Layer for Low Drain Lag and Leakage
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Solution Overview
Problem
Group III-nitride high-electron mobility transistors (HEMTs) face issues with drain lag effect and high leakage current due to the use of deep level impurities like Fe and C, which affect performance in high power and RF applications.
Innovation Solution
Incorporating a buried p-type layer with a higher bandgap than the buffer layer, reducing drain lag effect while minimizing leakage current, achieved through ion implantation and annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If deep level impurities (Fe or C) are used in the buffer layer to minimize leakage current, then leakage current is reduced, but drain lag effect increases
Solution Approach 1:
The buffer layer is segmented into multiple regions with different impurity concentrations. A first region contains deep level impurities (Fe or C) at concentrations of 1×10^16 to 1×10^18 atoms/cm³ to reduce leakage current, while a second region has lower impurity concentrations to minimize drain lag effect. This spatial segmentation allows both contradictory requirements to be satisfied in different parts of the same layer.
Solution Approach 2:
Different regions of the buffer layer are assigned different local qualities in terms of impurity concentration. The first region (closer to the AlGaN barrier layer) has higher deep level impurity concentration optimized for leakage current suppression, while the second region (deeper in the buffer) has lower concentration to reduce drain lag. This local quality variation resolves the contradiction between leakage reduction and drain lag minimization.
2Reliability
If high purity buffer layers without Fe or C are used to eliminate drain lag effect, then drain lag effect is eliminated, but leakage current increases
Solution Approach 1:
The buffer layer is divided into functional zones: a first region with controlled deep level impurity concentration (1×10^16 to 1×10^18 atoms/cm³) to suppress leakage current, and a second region with lower impurity concentration to minimize drain lag effect. This segmentation enables the device to achieve both low leakage and reduced drain lag without using completely pure buffer material.
Solution Approach 2:
The impurity concentration parameter is varied spatially within the buffer layer rather than maintaining a uniform concentration. By controlling the deep level impurity concentration in the first region at 1×10^16 to 1×10^18 atoms/cm³ and having lower concentration in the second region, the device optimizes both leakage current and drain lag characteristics through parameter gradient control.
3Reliability
If overlapping gate structures or field plates are used to modify electric field, then performance is improved, but device complexity increases
Solution Approach 1:
Instead of modifying the physical structure with overlapping gates or field plates, the invention changes the electrical parameters by controlling impurity concentration distribution in the buffer layer. The deep level impurity concentration is adjusted in different regions to modify the electric field characteristics and charge distribution, achieving performance improvement through parameter optimization rather than structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buried p-type layer optimizes breakdown voltage, reduces drain lag, and enables high voltage capability with compact device structures suitable for power switching and high power RF applications.
Implementation Method 1
Due to the high electric fields existing in these devices at high voltages and currents, charge trapping can lead to reduced performance.
Implementation Method 2
Ion implantation and annealing processes
Data Source
AI summary
An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.