GaN HEMT Closed Ring Gate Layout for Breakdown Voltage
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Solution Overview
Problem
Conventional GaN HEMT devices experience device breakdown due to high electric fields at the gate terminals, which limits their breakdown voltage and reliability, especially under high-voltage operations.
Innovation Solution
A novel layout design featuring a closed ring gate structure with intersecting source and drain fingers and arc-shaped corners, which increases the total gate width within a unit area, reduces point discharge, and distributes the electric field uniformly, thereby enhancing breakdown voltage and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional linear-type gate structure is used, then device structure is simple, but electric field concentrates at gate terminals causing breakdown
Solution Approach 1:
The gate structure is designed with arc-shaped corners instead of sharp angles. The arc radius R is specifically chosen to be between 0.5-2.0 times the gate width W, which smooths the electric field distribution at the gate terminals and prevents field concentration that would lead to breakdown.
Solution Approach 2:
The gate is divided into multiple segments or fingers that are distributed across the device area. This segmentation increases the total effective gate width while distributing the electric field more evenly, preventing concentration at any single point and improving breakdown voltage.
2Productivity
If gate width is increased to increase saturation current, then maximum saturation current increases, but device area increases reducing wafer utilization
Solution Approach 1:
The gate structure transitions from a conventional linear one-dimensional arrangement to a two-dimensional distributed finger configuration. Multiple gate fingers are arranged in parallel, increasing the total effective gate width and thus the saturation current without proportionally increasing the overall device footprint, improving wafer utilization.
Solution Approach 2:
The gate is segmented into multiple fingers that can be arranged in a compact parallel configuration. This segmentation increases the total gate width within a smaller area, thereby increasing saturation current while maintaining efficient use of wafer space.
3Reliability
If arc-shaped corners are added to gate structure, then electric field distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The arc radius R is defined as a specific parameter range (0.5-2.0 times gate width W) that balances electric field distribution improvement with manufacturability. This parameter optimization ensures adequate field smoothing while keeping the fabrication process within standard capabilities.
Data Source
AI summary
The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain.