Recessed-Gate GaN HEMT Barrier Structure for Current Collapse Suppression
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Solution Overview
Problem
Dynamic current collapse and parasitic effects limit the output power and efficiency of Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs), especially when scaled for higher frequency operations, due to electron trapping at the surface and interfaces of the epitaxial structure, constraining the device design and fabrication process.
Innovation Solution
The implementation of recessed-gate GaN-HEMTs with doped barrier layers and a round gate foot corner configuration, which includes a GaN buffer layer, AlGaN channel layer, undoped AlN interlayer, and Si-doped AlGaN barrier layers, reduces electron trapping and parasitic effects, enabling high-frequency power performance with suppressed dynamic knee current collapse, high power density, and high power added efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional GaN HEMT structures are used, then device simplicity is maintained, but dynamic current collapse and parasitic effects limit output power and efficiency
Solution Approach 1:
The barrier layer is divided into multiple segments: an undoped first barrier layer and a doped second barrier layer. This segmentation allows the undoped region to maintain high electron mobility while the doped region compensates for electron trapping effects, thereby resolving the dynamic current collapse issue while maintaining high output power capability
Solution Approach 2:
The patent employs a composite barrier structure combining undoped AlGaN and Si-doped AlGaN layers. This composite approach leverages the high electron mobility of undoped regions and the electron trapping compensation of doped regions, eliminating dynamic current collapse while preserving power output
2Power
If barrier layers are doped to reduce electron trapping, then power added efficiency is improved, but parallel conduction may occur at high doping concentrations
Solution Approach 1:
Doping is applied locally only in the second barrier layer region, while the first barrier layer remains undoped. This localized doping strategy reduces electron trapping at the cap layer interface without inducing parallel conduction, thereby improving power added efficiency while avoiding harmful side effects
Solution Approach 2:
The patent optimizes the doping concentration parameter in the second barrier layer to be greater than the electron trap density at the cap layer interface. This parameter change ensures effective compensation of electron trapping effects while maintaining the doping level below the threshold for parallel conduction, achieving high power added efficiency without harmful conduction paths
3Object-affected harmful factors
If gate foot corners are made sharp, then manufacturing is simpler, but electric field concentration increases causing higher parasitic effects
Solution Approach 1:
The gate foot corners are designed with rounded geometry instead of sharp corners. This curvature eliminates electric field concentration at the gate feet, reducing parasitic effects and improving device performance. The rounding radius is optimized to balance parasitic reduction with manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high power density, high power added efficiency, and high gain linearity, addressing the limitations of current GaN HEMTs by reducing electron trapping and parasitic effects, thereby enhancing performance for W-band applications without the need for additional field plates.
Implementation Method 1
electron trapping at the surface and interfaces of the epitaxial structure
Implementation Method 2
The first barrier layer has a first doping concentration defined as a two dimensional electron gas (2DEG) density in a source access region and a drain access region
Data Source
AI summary
A high electron mobility transistor comprising a substrate. The substrate comprising: a buffer layer, a channel layer disposed on the buffer layer, an interlayer disposed on the channel layer, a spacer layer, and a first barrier layer between the spacer layer and a cap layer, the spacer layer is between the interlayer and the first barrier layer. The high electron mobility transistor comprises a source electrode disposed on the channel, a drain electrode disposed on the channel, and a gate electrode disposed between the source electrode and the drain electrode, the gate electrode defining a longitudinal portion extending through the capping layer, wherein a distal end of the longitudinal portion is in contact with the first barrier layer defines an external fillet between the distal end and the longitudinal portion.