GaN-HEMT Gate Drive Biasing for Dead-Time Loss Reduction
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Solution Overview
Problem
In switching circuits using GaN-HEMTs, reverse currents during dead times lead to significant losses due to high reverse voltages, which are not effectively managed by existing gate drive circuits.
Innovation Solution
A gate drive circuit for GaN-HEMTs that applies a bias voltage lower than the gate threshold voltage during dead times to reduce reverse voltage, integrated with high-side and low-side drivers capable of multiple voltage levels, including 0 V, high-level, and bias voltage, to minimize losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dead time is inserted to prevent through-current when both high-side and low-side transistors are turned on, then transistor safety is improved, but reverse current flows through the low-side transistor during dead time causing significant power loss
Solution Approach 1:
The patent applies a bias voltage (negative voltage relative to source) to the gate of the low-side transistor during dead time, changing the electrical parameter of gate voltage from 0V or positive to negative. This parameter change reduces the reverse voltage across the transistor body diode during reverse current flow, thereby reducing power loss while maintaining the protective dead time function
2Device complexity
If existing gate drive circuits are used during dead time, then circuit simplicity is maintained, but reverse voltage is not effectively managed leading to high power consumption in GaN-HEMTs
Solution Approach 1:
The patent implements dynamic gate voltage control where the gate drive circuit switches between different voltage levels (0V, positive voltage, and negative bias voltage) based on the operational state. During dead time, the circuit dynamically applies a negative bias voltage to the gate, adapting the electrical conditions to minimize power loss while maintaining transistor safety
Solution Approach 2:
The patent applies a negative bias voltage to the gate before and during dead time to preemptively reduce the reverse voltage across the transistor. This preliminary action prevents the full reverse voltage from appearing across the transistor body diode, thereby reducing power loss before reverse current can flow
Data Source
AI summary
A gate drive circuit for a switching circuit including high-side and low-side transistors which are GaN-HEMTs (High Electron Mobility Transistors), includes: a high-side driver driving the high-side transistor; and a low-side driver driving the low-side transistor, wherein the low-side driver is configured to be capable of applying 0 V, a high-level voltage higher than a gate threshold voltage of the low-side transistor, and a bias voltage lower than the gate threshold voltage between a gate and a source of the low-side transistor, and the low-side driver is configured to apply the bias voltage between the gate and the source of the low-side transistor during a dead time inserted during transition from a high-level output state where the high-side transistor is turned on and the low-side transistor is turned off to a low-level output state where the high-side transistor is turned off and the low-side transistor is turned on.