GaN HEMT Doping Patterning for Lower On-Resistance
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Solution Overview
Problem
Existing semiconductor fabrication methods for AlGaN/GaN High Electron Mobility Transistors (HEMTs) face challenges in reducing on-resistance and improving high-frequency performance due to limitations in doping layer formation and etching processes.
Innovation Solution
A semiconductor device fabrication method involving electron beam lithography to pattern N-type doping layers, eliminating the need for additional mask layers and reducing the gap width between source and drain doping parts, while using atomic layer deposition for protective layers and atomic layer etching for gate electrodes to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography methods are used to pattern N-type doping layers, then the fabrication process is simpler, but the gap width between source and drain doping parts cannot be sufficiently reduced
Solution Approach 1:
The patent replaces conventional optical lithography with electron beam lithography to pattern the N-type doping layer. This substitution enables precise control of the gap width between source and drain doping parts down to 100 nm or less, achieving the required manufacturing precision while managing the increased process complexity through advanced fabrication techniques.
2Reliability
If the gap width between source and drain doping parts is reduced, then on-resistance decreases, but conventional methods cannot achieve sufficient reduction
Solution Approach 1:
The patent employs electron beam lithography instead of conventional optical lithography to achieve precise patterning of the N-type doping layer with gap widths of 100 nm or less. This enables sufficient reduction of on-resistance while maintaining controllable manufacturing precision through advanced lithographic techniques.
3Manufacturing precision
If additional mask layers are added to achieve precise patterning, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent replaces the multi-layer mask approach with electron beam lithography, which achieves precise patterning directly through electronic beam control. This eliminates the need for additional mask layers while maintaining high manufacturing precision, thereby reducing device complexity.
4Productivity
If the cutoff frequency is increased for high-frequency applications, then performance improves, but conventional fabrication methods limit the achievable frequency
Solution Approach 1:
The patent uses atomic layer etching instead of conventional etching methods to form the gate electrode with precise dimensional control. This enables the achievement of higher cutoff frequencies required for high-frequency applications while maintaining the manufacturing precision needed for optimal device performance.
Solution Approach 2:
The patent employs atomic layer deposition to form protective layers with precisely controlled thickness and composition. This parameter control enables optimization of the device structure for high-frequency operation, achieving improved cutoff frequency while maintaining the required manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces on-resistance and increases the cutoff frequency of the semiconductor device by shortening the gap width between source and drain doping parts and optimizing the formation of gate electrodes, thereby improving high-frequency application capabilities.
Implementation Method 1
patterning the N type doping layer by electron beam lithography to form a source N type doping part and a drain N type doping part
Implementation Method 2
using atomic layer deposition for protective layers
Implementation Method 3
atomic layer etching for gate electrodes to enhance performance
Data Source
AI summary
The disclosure provides a semiconductor device and a fabrication method thereof and the fabrication method includes following steps: forming a semiconductor stack on a substrate; forming a N type doping layer on the semiconductor stack; patterning the N type doping layer by electron beam lithography to form a source N type doping part and a drain N type doping part; forming a source electrode on the source N type doping part; forming a drain electrode on the drain N type doping part; and forming a gate electrode that is located between the source N type doping part and the drain N type doping part on the semiconductor stack.