GaN HEMT Dual p-type Layer Current Density Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
GaN-based HEMTs with a p-type GaN layer for normally-off operation face issues such as current collapse and deterioration due to lattice distortion and etching damage, leading to high current density concentrations and electro-migration, which affect their longevity and performance.
Innovation Solution
A compound semiconductor device structure is developed with a first and second p-type semiconductor layer, where the second p-type semiconductor layer has a higher resistance metal film in contact with the gate electrode side, reducing current density concentration and suppressing etching damage by maintaining a portion of the p-type semiconductor layer between the gate and source/drain electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a p-type GaN layer is formed between the gate electrode and the electron supply layer to achieve normally-off operation, then the device can operate in normally-off mode, but current collapse and characteristic deterioration occur due to lattice distortion and etching damage
Solution Approach 1:
The patent divides the single p-type GaN layer into two separate layers: a first p-type GaN layer between the gate electrode and electron supply layer for normally-off operation, and a second p-type GaN layer between the electron supply layer and source/drain electrodes for protecting against etching damage. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between achieving normally-off operation and maintaining device reliability.
Solution Approach 2:
The first p-type GaN layer acts as an intermediary between the gate electrode and the electron supply layer, enabling normally-off operation by controlling the flow of electrons. Meanwhile, the second p-type GaN layer serves as a protective intermediary that shields the electron supply layer from etching damage during manufacturing, thus maintaining device stability.
2Productivity
If the device is miniaturized to improve integration density, then productivity increases, but the device cannot stand for long-period use due to increased current density concentration and electro-migration
Solution Approach 1:
The patent applies different properties to different regions by creating a dual-layer p-type GaN structure with distinct functions. The second p-type GaN layer under the source/drain electrodes has higher resistance characteristics that specifically address current density concentration in the miniaturized device regions, while the first layer maintains the normally-off operation capability. This local quality differentiation allows miniaturization without sacrificing device longevity.
3Device complexity
If a single p-type GaN layer is used to achieve normally-off operation, then the device structure is simplified, but etching damage occurs during manufacturing leading to characteristic deterioration
Solution Approach 1:
The patent segments the protective function from the operation control function by creating two separate p-type GaN layers. The second layer specifically protects against etching damage during manufacturing processes, while the first layer maintains the normally-off operation. This segmentation resolves the contradiction by adding a specialized protective layer without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the stability and longevity of GaN-based HEMTs by reducing current density concentration and preventing electro-migration, thereby maintaining device performance and preventing characteristic deterioration.
Implementation Method 1
a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film
Implementation Method 2
reducing current density concentration and suppressing etching damage by maintaining a portion of the p-type semiconductor layer between the gate and source/drain electrodes
Data Source
AI summary
An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.