Normally-Off GaN HEMT Field Plate Layout for Lower Gate-Drain Capacitance

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Solution Overview

Problem

AlGaN/GaN high-electron-mobility transistors (HEMTs) of the normally-off type face limitations in maximum operating frequency due to high gate-to-drain capacitance and associated charge requirements, hindering their use in high-frequency applications.

Innovation Solution

The integration of a heterojunction integrated device with a specific insulating field structure and field plate configuration, utilizing multiple dielectric layers with varying thicknesses and materials, reduces gate-to-drain capacitance by precise control of the insulating field structure's thickness and profile, enhancing switching speed and frequency capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a p-doped GaN gate region is formed in a normally-off AlGaN/GaN HEMT, then the device achieves normally-off operation with simplified driving circuits, but the gate-to-drain capacitance increases, limiting the maximum operating frequency

Engineering Contradiction:
Improvenormally-off operation capabilityVSAvoidmaximum operating frequency
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The gate structure is segmented into multiple regions with different doping profiles and depths. The p-GaN gate is divided into a first p-GaN gate region with higher doping concentration and a second p-GaN gate region with lower doping concentration, allowing independent optimization of threshold voltage control and capacitance reduction for each segment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate structure are assigned different local properties: the first p-GaN gate region has higher doping concentration (1e18 to 1e19 atoms/cm³) for strong threshold control, while the second p-GaN gate region has lower doping concentration (1e16 to 1e17 atoms/cm³) to reduce charge storage and capacitance, with each region having optimized depth and width parameters

Inventive Principle:
Principle #3Local quality

2Speed

If the insulating field structure thickness is reduced to lower gate-to-drain capacitance, then switching speed improves, but breakdown resistance may be compromised

Engineering Contradiction:
Improveswitching speedVSAvoidbreakdown resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The insulating field structure employs a graded thickness profile where the first portion has reduced thickness (5-20 nm) near the gate for low capacitance, while the second portion has increased thickness (20-50 nm) extending toward the drain for enhanced breakdown resistance, with the transition zone optimized to maintain field distribution

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The insulating field structure uses composite dielectric materials with different properties: a first dielectric material (such as Al2O3 or HfO2) for the first portion providing high breakdown field, and a second dielectric material (such as SiO2 or Si3N4) for the second portion providing mechanical stability and field distribution

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces gate-to-drain capacitance and accumulated charge, improving the performance of normally-off HEMTs by allowing for higher frequency operations while maintaining breakdown resistance.

Implementation Method 1

The integration of a heterojunction integrated device with a specific insulating field structure and field plate configuration, utilizing multiple dielectric layers with varying thicknesses and materials, reduces gate-to-drain capacitance by precise control of the insulating field structure's thickness and profile

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20240313102A1Normally-off heterojunction integrated device and method for manufacturing an integrated device
Publication Date: 2024.09.19 STMICROELECTRONICS SRL
  • US20240313102A1 patent drawing
  • US20240313102A1 patent drawing
  • US20240313102A1 patent drawing

AI summary

An integrated power device includes a heterostructure, having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region, arranged on the barrier layer between the source contact and the drain contact. An insulating field structure is arranged on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material, selectively etchable with respect to the first dielectric material on the first dielectric region. On a side of the insulating field structure towards the gate region, the field plate is in contact with the first dielectric region.