GaN HEMT Gate Structure with Segmented Barrier for Low On-Resistance
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Solution Overview
Problem
Conventional GaN High Electron Mobility Transistor (HEMT) fabrication methods on silicon substrates face issues such as p-dopant out-diffusion and migration into the 2DEG channel region, leading to increased on-resistance and dynamic on-resistance, as well as difficulties in selectively etching the p-GaN layer, resulting in etch damage and reduced threshold voltage control.
Innovation Solution
A method involving selective area growth of p-doped GaN using a dielectric passivation layer as a p-dopant diffusion barrier, with lower temperature processing and structured AlxGa1-xN barrier layer thickness and aluminum percentage profiles to decouple threshold voltage and on-resistance, allowing for independent control of device parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If blanket deposition of p-doped GaN layer is performed at high temperature (1000-1100 C) to form the gate region, then the p-GaN layer can be uniformly deposited, but p-dopant out-diffuses and migrates into the 2DEG channel region causing increased on-resistance and dynamic on-resistance
Solution Approach 1:
The patent segments the GaN layer formation into two distinct steps: first depositing a blanket undoped GaN layer, then selectively doping only the gate region after patterning. This avoids high-temperature doping that causes dopant diffusion into the channel, while still achieving uniform gate region coverage through the initial blanket deposition step.
Solution Approach 2:
The patent performs preliminary deposition of an undoped GaN layer before selective doping. This preliminary layer provides a uniform base that prevents dopant diffusion into the channel during subsequent selective doping processes, while ensuring consistent material quality across the entire device area.
2Manufacturing precision
If the blanket p-GaN layer is etched to leave p-GaN only in the gate region, then the gate structure can be defined, but etch damage occurs to the underlying AlGaN barrier layer and epitaxial stack
Solution Approach 1:
The patent extracts the doping step from the layer formation process. Instead of depositing doped material and then removing it from non-gate areas, the method deposits undoped material uniformly and then adds dopants only where needed. This eliminates the etching step that causes damage to underlying layers.
Solution Approach 2:
The patent converts the potential harm of requiring selective p-GaN deposition into a benefit by using a two-step process that first ensures uniform coverage and then selectively activates doping only in the gate region. This approach turns the challenge of selective formation into an advantage by ensuring both uniformity and precision without damaging etching.
3Reliability
If increasing the aluminium content and thickness of the AlxGa1-xN barrier layer is performed to reduce Rdson, then the on-resistance decreases, but the threshold voltage drops to zero causing depletion mode operation
Solution Approach 1:
The patent applies local quality by creating a spatially varying Al composition profile in the barrier layer. The barrier layer has higher Al content near the gate where strong field effect is needed for low on-resistance, and lower Al content in the channel region to maintain appropriate threshold voltage. This local variation allows simultaneous optimization of both parameters.
Solution Approach 2:
The patent changes the Al composition parameter x in AlxGa1-xN as a function of position and depth. By varying the Al content gradient and barrier thickness, the patent independently controls the threshold voltage (affected by overall barrier properties) and on-resistance (affected by local field effect near the gate), resolving the trade-off between these two parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces p-dopant out-diffusion, minimizes etch damage, and provides improved control over on-resistance and threshold voltage, enhancing the performance of GaN HEMT devices by reducing the on-resistance and dynamic on-resistance while maintaining reliable E-mode operation.
Implementation Method 1
providing a dielectric passivation layer as a p-dopant diffusion barrier
Implementation Method 2
selective area growth of p-doped GaN
Data Source
AI summary
GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).