GaN HEMT Gate Region Conductive Coating for On-State Resistance
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Solution Overview
Problem
Gallium nitride normally-off high electron mobility transistors (HEMTs) face challenges with high on-state resistance, which degrades their electric performance due to conduction paths that electrons follow to bypass the gate region, and they struggle to achieve sufficient threshold voltage for various applications.
Innovation Solution
The transistor design includes a gate region with a conductive layer coating its sides, a multilayer structure with P-type doped sub-layers, and inclined gate electrode sides to facilitate electron flow, reducing on-state resistance and allowing for higher threshold voltage by modifying the doping rate and using a conductive layer to enhance electron mobility and suppress trapping phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gallium nitride normally-off HEMT structure is used, then the transistor can achieve normal switching operation, but it exhibits high on-state resistance which degrades electric performance
Solution Approach 1:
The patent introduces a third dimension by coating the lateral sides of the gate region with a conductive layer. This lateral conduction path supplement reduces the effective resistance without interfering with the vertical switching operation, thereby resolving the contradiction between maintaining normal operation and reducing on-state resistance.
Solution Approach 2:
The conductive layer is segmented into multiple regions: a first portion coating the side in front of the source electrode and a second portion coating the side in front of the drain electrode. This segmentation allows independent optimization of electron injection at the source side and collection at the drain side, effectively reducing overall on-state resistance while maintaining proper transistor operation.
2Object-affected harmful factors
If the gate region structure is modified to reduce on-state resistance, then electric performance improves, but the threshold voltage control becomes challenging
Solution Approach 1:
The conductive layer is applied locally only to the lateral sides of the gate region, not throughout the entire device. This localized modification reduces on-state resistance through lateral conduction while leaving the vertical gate control mechanism intact, thus maintaining threshold voltage control without excessive device complexity.
Solution Approach 2:
The conductive layer acts as an intermediary element that provides an alternative conduction path lateral to the gate. It mediates between the source and drain regions by facilitating electron flow around the gate barrier, reducing on-state resistance while the gate electrode itself continues to control the threshold voltage through its vertical field effect.
3Productivity
If electrons follow conduction paths to bypass the gate region, then the transistor can conduct current, but the on-state resistance remains high
Solution Approach 1:
The patent adds a lateral dimension to the conduction path by coating the gate sides with conductive material. Electrons can now travel laterally along the conductive layer from the source side to the drain side, creating a parallel conduction path that reduces overall resistance while maintaining current conduction capability.
Solution Approach 2:
The device structure becomes composite, combining the original vertical conduction path through the semiconductor layers with a new lateral conduction path through the conductive coating. This composite structure allows electrons to utilize both vertical and lateral paths, effectively reducing on-state resistance while maintaining proper current conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly decreases the on-state resistance and increases the threshold voltage, improving the electric performance of the transistors by enhancing electron mobility and reducing electron trapping, thus addressing the limitations of existing HEMTs.
Implementation Method 1
a second electrically-conductive layer, coating at least one of the sides of said gate region... enhancing electron mobility and reducing electron trapping
Implementation Method 2
a multilayer structure with P-type doped sub-layers... modifying the doping rate and using a conductive layer to enhance electron mobility
Data Source
AI summary
A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.