GaN HEMT Gate Fin Doping for Normally-Off Leakage Control
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Solution Overview
Problem
High-electron-mobility field effect transistors (HEMTs) face challenges in achieving a normally-off configuration and reducing gate leakage current, which affects power consumption and performance, due to the high electron mobility and self-conducting nature of the heterojunction configuration.
Innovation Solution
A fin-shaped gate configuration with a doped type III-nitride semiconductor material surrounding the gate fin, incorporating current blocking devices such as Schottky diodes and PIN diodes to prevent carrier flow and mitigate gate leakage, while a layered stack of GaN-based layers with varying aluminum content forms two-dimensional charge carrier gas channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heterojunction configuration is used to achieve high electron mobility, then conduction performance is improved, but the device becomes self-conducting (normally-on) and gate leakage current increases
Solution Approach 1:
The patent changes the electrical parameters of the gate structure by introducing doped semiconductor regions with specific doping types and concentrations. The first doped region has a first doping type and concentration, while the second doped region has a second doping type and concentration, creating parameter variations that enable normally-off operation and reduce gate leakage while preserving high electron mobility in the channel
Solution Approach 2:
The patent applies different doping characteristics to different locations within the gate structure. The doped semiconductor regions are positioned at specific locations (first and second doped regions with different doping types and concentrations) to create localized electrical properties that control carrier flow, enabling the gate to effectively deplete the channel and prevent leakage current without affecting the overall high mobility channel performance
2Ease of operation
If additional features are added to achieve normally-off configuration, then device control is improved, but device complexity increases
Solution Approach 1:
The patent combines the gate structure with doped semiconductor regions integrated directly into the gate electrode or gate insulator interface. This merging of the gate control structure with the doping regions creates a unified device architecture that achieves normally-off operation without adding separate complex control mechanisms, thereby improving ease of operation while minimizing increases in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively depletes the two-dimensional charge carrier gas in all directions, providing improved ON-OFF control and reducing gate leakage current, resulting in enhanced electrical characteristics and reduced power consumption.
Implementation Method 1
each of the two-dimensional charge carrier gas channels in the plurality being formed by a heterojunction between two regions of type III-nitride semiconductor material with different bandgaps
Implementation Method 2
a two-dimensional electron gas (2DEG) arises near the interface between the AlGaN barrier layer and the GaN channel layer
Implementation Method 3
the gate structure is configured to control a conductive connection between the source and drain contacts by controlling a conductive state of each one of the two-dimensional charge carrier gas channels
Implementation Method 4
one or more current blocking devices that are configured to prevent carriers from flowing into or out of the region of doped type III-nitride semiconductor material
Implementation Method 5
current blocking devices such as Schottky diodes and PIN diodes to prevent carrier flow
Data Source
AI summary
A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.