GaN HEMT Buried P-Type Gate Structure for Gate Lag Suppression
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Solution Overview
Problem
Gallium nitride high-electron mobility transistors (HEMTs) suffer from gate lag effects and other performance issues due to traps in the buffer layers, particularly at high negative gate voltages, which adversely affect their performance.
Innovation Solution
Incorporating a buried p-type layer with a higher bandgap than the buffer layer, extending towards the source and drain sides, and connecting it to the gate or a separate negative gate voltage to mitigate trapping effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If buffer layers with traps are used to achieve desired breakdown voltage, then breakdown voltage is improved, but gate lag effect increases
Solution Approach 1:
A p-type layer is introduced as an intermediary component between the buffer layer and the active device region. This p-type layer acts as a mediator that provides the necessary electrical breakdown characteristics while preventing charge trapping that causes gate lag effect, thus resolving the contradiction between achieving high breakdown voltage and maintaining device reliability
Solution Approach 2:
The device structure is segmented into distinct functional regions: a buffer layer for mechanical support and a separate p-type layer for electrical breakdown control. This segmentation allows each layer to optimize its specific function without the negative interactions present in integrated trap-based designs
2Ease of operation
If high negative gate voltages are applied to achieve desired device operation, then device control is improved, but gate lag effect becomes more prevalent
Solution Approach 1:
The p-type layer is positioned and configured in advance to counteract the harmful effects of high negative gate voltages before they can cause significant gate lag effect. The layer pre-establishes an electrical environment that mitigates charge trapping during high-voltage operation, allowing full utilization of gate voltage control range without suffering from lag effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure significantly reduces or eliminates gate lag effects, enhancing the performance of GaN HEMTs for high power and high frequency applications.
Implementation Method 1
a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer includes a higher bandgap than a bandgap of the group III-Nitride buffer layer
Data Source
AI summary
An apparatus to address gate lag effect and/or other negative performance includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at least in the substrate. In particular, the p-region extends toward a source side of the substrate; and the p-region extends toward a drain side of the substrate.