GaN HEMT Gate Passivation Layer for Leakage and Trapping Control

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Solution Overview

Problem

Enhancement-mode high electron mobility transistors (HEMTs) with a p-type doped GaN layer face issues with gate reliability and surface trapping, particularly in high voltage applications, due to the weak interface between the gate metal and p-type GaN, which leads to early onset of gate degradation.

Innovation Solution

Incorporating a first passivation layer made of materials with ultra-wide bandgap and high-k properties, such as AlN, InAlN, SiO2, Al2O3, SiN, HfO2, TiO2, or Ga2O3, or combinations thereof, sandwiched between the first metal electrode contact and the gate structure to provide an extra barrier for electron trapping and hole injection, thereby improving gate reliability and minimizing surface trapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a p-type doped GaN layer is used in enhancement-mode HEMT, then the transistor can be commercially available and functional, but gate reliability deteriorates and surface trapping increases due to the weak interface between gate metal and p-type GaN

Engineering Contradiction:
Improvegate reliabilityVSAvoidsurface trapping
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An AlN layer is introduced as an intermediary between the gate metal and the p-type GaN layer. This AlN interface layer acts as a mediator that prevents direct contact between the gate metal and p-type GaN, thereby eliminating the weak interface problem while maintaining the enhancement-mode functionality of the HEMT.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate stack is designed as a composite structure combining multiple materials: gate metal, AlN interface layer, and p-type GaN layer. This composite structure leverages the advantages of each material - the gate metal for electrical contact, the AlN for interface quality and barrier properties, and the p-type GaN for device functionality - to achieve both low contact resistance and high gate reliability.

Inventive Principle:
Principle #40Composite materials

2Device complexity

If the gate metal directly contacts the p-type GaN layer, then the device structure is simple, but the interface becomes a weak point allowing early onset of gate degradation

Engineering Contradiction:
Improveinterface structureVSAvoidgate degradation resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The AlN layer serves as an intermediary that is specifically positioned at the critical gate interface. This thin layer does not significantly increase device complexity while providing substantial improvement in gate degradation resistance by preventing direct interaction between gate metal and p-type GaN.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The introduction of the AlN layer changes the interface parameters - specifically the contact resistance and interface quality - between the gate metal and p-type GaN. This parameter change transforms the weak interface into a robust interface with controlled electrical properties.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If passivation techniques are applied to minimize surface trapping, then surface trapping is reduced, but the interface between gate metal and p-type GaN remains unprotected and gate degradation occurs early

Engineering Contradiction:
Improvesurface trappingVSAvoidgate degradation
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The AlN interface layer acts as a protective intermediary that addresses both surface trapping and gate degradation simultaneously. By positioning this layer at the gate interface, it provides protection against both surface-related issues and direct gate degradation mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate interface is segmented into distinct functional layers: the gate metal layer, the AlN interface layer, and the p-type GaN layer. This segmentation allows each layer to perform its specific function - electrical contact, interface protection, and device operation - independently, resolving the conflicting requirements.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The introduction of the passivation layer significantly enhances gate reliability by reducing gate leakage and suppressing current collapse, with improvements in gate leakage by 1-2 orders of magnitude and maintaining threshold voltage stability.

Implementation Method 1

Materials having ultra-wide bandgap and high-k properties such as AlN, InAlN and AlGaN

Methodology Applied
Scientific EffectUltra-wide bandgap:

Implementation Method 2

Materials having ultra-wide bandgap and high-k properties such as AlN, InAlN and AlGaN, SiO2, Al2O3, SiN, HfO2, TiO2, or Ga2O3

Methodology Applied
Scientific EffectHigh-k dielectric property: Dielectric Permittivity

Implementation Method 3

When the first passivation layer of the present disclosure is on top of the barrier layer of the GaN epi layer, it also minimizes electron trapping in the surface passivation and therefore suppresses current collapse.

Methodology Applied
Scientific EffectSurface passivation:

Data Source

PatentUS12543363B2High electron mobility transistor and high electron mobility transistor forming method
Publication Date: 2026.02.03 HIPER SEMICONDUCTOR INC
  • US12543363B2 patent drawing
  • US12543363B2 patent drawing
  • US12543363B2 patent drawing

AI summary

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.