GaN HEMT Gate Recess Structure for Leakage Suppression
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Solution Overview
Problem
Semiconductor devices using GaN-based materials face issues with parasitic leakage paths and increased leakage current due to process-related defects, which affect their breakdown voltage and on-resistance performance.
Innovation Solution
A semiconductor device design incorporating a GaN-based high electron mobility transistor (HEMT) with a gate/recess structure, where the gate electrode is embedded in a recess formed in the semiconductor layer, and a device isolation region is created using ion implantation, ensuring the gate electrode's end portion is within the recess, reducing overlap and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GaN-based semiconductor is used to improve breakdown voltage and reduce on-resistance, then the trade-off relation between breakdown voltage and on-resistance is improved, but parasitic leakage paths are formed and leakage current increases
Solution Approach 1:
The gate electrode is segmented into multiple sections (first gate electrode and second gate electrode) separated by a groove, which divides the continuous gate structure into discrete segments. This segmentation prevents the formation of continuous parasitic leakage paths along the gate electrode while maintaining the electrical functionality of the device.
Solution Approach 2:
A groove is extracted or removed from the semiconductor layer to create a physical separation between adjacent gate electrodes. This extracted portion acts as an isolation structure that eliminates parasitic leakage paths without requiring additional insulating materials or complex processing steps.
2Speed
If gate electrode is extended to reduce parasitic capacitance, then device speed is improved, but leakage current increases due to overlap with semiconductor layer
Solution Approach 1:
The gate electrode is divided into multiple segments with gaps between them, allowing the gate to extend closer to the source and drain regions without creating continuous parasitic leakage paths. The segmentation enables speed improvement while controlling leakage.
Solution Approach 2:
The groove structure creates localized isolation regions specifically at critical areas where parasitic leakage occurs, while maintaining continuous gate control in other regions. This local quality change allows selective suppression of leakage without compromising overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses leakage current, enhances device speed, and maintains normally-off operation while improving the reliability of the gate insulating film, thereby improving the trade-off between breakdown voltage and on-resistance.
Implementation Method 1
a gate insulating film provided on a surface of the recess
Implementation Method 2
a device isolation region created using ion implantation
Data Source
AI summary
A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.