GaN HEMT Gate Metallization Stack for Leakage Reduction

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Solution Overview

Problem

In enhancement-mode high electron mobility transistors (HEMTs) with p-type doped GaN gate electrodes, the contact etch process leads to a roughened surface, increasing gate current and parasitic leakage, and existing contact types either result in negative threshold voltage shifts or high gate leakage, making it difficult to achieve a balance between both.

Innovation Solution

A gate metallization stack is formed over the gate electrode before patterning, with conductive sidewall spacers aligned to the crystal plane, using materials like TiN and AlCu to balance threshold voltage and gate current, and the thickness of the lower film in the metallization stack is optimized to minimize contact resistance and leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a contact etch process is used to form a contact opening to the gate electrode, then the contact opening is defined to expose the gate electrode, but the exposed surface of the p-type doped GaN becomes roughened, causing higher gate current

Engineering Contradiction:
Improvecontact opening formationVSAvoidgate current
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A metal-containing layer is deposited over the gate electrode layer before the contact opening is etched. This preliminary deposition protects the gate electrode surface from etching damage, maintaining surface smoothness and preventing increased gate current while still allowing the contact opening to be formed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A metal-containing layer is introduced as an intermediary between the gate electrode and the etch process. This intermediate layer absorbs the harmful effect of the etch, preventing direct contact between the etchant and the gate electrode surface, thus avoiding surface roughening.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If metalized contact is formed within the contact opening of the interlevel dielectric layer, then contact is made to the gate electrode, but significant parasitic gate leakage current occurs along the sidewall of the p-type doped gate electrode

Engineering Contradiction:
Improvecontact formationVSAvoidparasitic gate leakage current
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The metal-containing layer is deposited over the gate electrode layer before the contact opening etch is performed. This preliminary deposition ensures that the gate electrode surface is protected during etching, preventing sidewall roughening that would lead to parasitic leakage paths.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11721736B2Electronic device including a gate structure and a process of forming the same
Publication Date: 2023.08.08 SEMICON COMPONENTS IND LLC
  • US11721736B2 patent drawing
  • US11721736B2 patent drawing
  • US11721736B2 patent drawing

AI summary

An electronic device can include a gate structure. In an embodiment, the gate structure can include a gate electrode including a doped semiconductor material, a metal-containing member, a pair of conductive sidewall spacers. The first metal-containing member can overlie the gate electrode. The conductive sidewall spacers can overlie the gate electrode and along opposite sides of the first metal-containing member. In another embodiment, the gate structure can include a gate electrode, a first metal-containing member overlying the gate electrode, and a second metal-containing member overlying the first metal-containing member. The first metal-containing member can have a length that is greater than the length of the second metal-containing member and substantially the same length as the gate electrode.