Normally-Off GaN HEMT Gate Stack for Higher Threshold Voltage
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Solution Overview
Problem
Current GaN-based power devices face challenges in achieving high gate-withstand voltage and threshold voltage, particularly in the p-type cap layer solution, which limits their reliability and performance in high-voltage applications.
Innovation Solution
A high-threshold-voltage normally-off high-electron-mobility transistor is designed with a p-GaN (or p-InGaN or p-AlGaN) gate cap layer subjected to surface oxidation or a composite gate dielectric insertion layer, enhancing the conduction band position and increasing the gate withstand voltage and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type cap layer is grown on the gate to achieve normally-off operation, then the device safety and energy efficiency are improved, but the gate-withstand voltage and threshold voltage are reduced
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple layers including AlGaN barrier layer, p-GaN cap layer, and GaN buffer layer. This composite structure allows the device to achieve normally-off operation through the p-type cap layer while maintaining high gate-withstand voltage through the carefully engineered combination of materials with different properties, thus resolving the contradiction between reliability improvement and strength reduction
Solution Approach 2:
The patent applies local quality by creating a p-type doped region specifically at the gate cap layer while keeping other regions with different properties. The p-GaN cap layer is locally doped to achieve normally-off operation, while the underlying AlGaN barrier layer and GaN buffer layer maintain their intrinsic properties to support high voltage operation, thus resolving the contradiction between local functionality and overall strength
2Reliability
If a p-type cap layer is grown on the gate to achieve normally-off operation, then the device safety and energy efficiency are improved, but the threshold voltage is reduced
Solution Approach 1:
The patent utilizes parameter changes by adjusting the doping concentration and thickness of the p-GaN cap layer to achieve the desired threshold voltage. By carefully controlling these parameters, the device achieves normally-off operation with improved safety while maintaining an appropriate threshold voltage level, thus resolving the contradiction between reliability improvement and strength reduction
3Reliability
If the conduction band position is increased to improve gate withstand voltage and threshold voltage, then the device reliability is improved, but the on-current density may be reduced
Solution Approach 1:
The patent applies local quality by creating a p-type doped region specifically at the gate cap layer while keeping other regions with different properties. The p-GaN cap layer is locally doped to achieve normally-off operation, while the underlying AlGaN barrier layer and GaN buffer layer maintain their intrinsic properties to support high voltage operation, thus resolving the contradiction between local functionality and overall strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively improves the gate withstand voltage and threshold voltage of normally-off devices, achieving values greater than 20V and 2V respectively, while maintaining a large on-current density, thus addressing the limitations of existing technologies.
Implementation Method 1
p-GaN (or p-InGaN or p-AlGaN) gate cap layer subjected to surface oxidation
Implementation Method 2
spontaneous polarization and piezoelectric polarization charges at interfaces of the GaN-based heterojunctions (represented by AlGaN/GaN) would induce the generation of high-density Two-Dimensional Electron Gas (2DEG)
Implementation Method 3
composite gate dielectric insertion layer
Data Source
AI summary
A high-threshold-voltage normally-off high-electron-mobility transistor (HEMT) includes a nucleation layer and an epitaxial layer are grown sequentially on a substrate; a barrier layer, a source, and a drain above the epitaxial layer; the barrier layer and the epitaxial layer form a heterojunction structure, and the contact interface therebetween is induced by polarization charges to generate two-dimensional electron gas. The HEMT includes a passivation layer above the barrier layer; a gate cap layer above the gate region barrier layer; the upper part of the gate cap layer is subjected to surface plasma oxidation to form an oxide dielectric layer, or a single-layer or multiple gate dielectric insertion layer is directly deposited thereon. The HEMT includes a gate is located above the gate dielectric insertion layer; the gate is in contact with the passivation layer; and a field plate extends from the gate to the drain on the passivation layer.


