GaN HEMT Gate Trench Fabrication With Controlled Doped Region Depth

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Solution Overview

Problem

Existing methods for fabricating high electron mobility transistors (HEMTs) from GaN-based materials face challenges in achieving precise control over doped region formation, leading to excessive depth and potential performance issues due to direct ion implantation into the barrier layer, affecting device resistance and switching operations.

Innovation Solution

A method involving the formation of a buffer and barrier layer, followed by a hard mask and ion implantation through the mask to create a doped region in both layers, with subsequent etching and dielectric layer formation to construct a gate electrode and source/drain electrodes, allowing for controlled trench formation and reduced doped region depth, thereby improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If direct ion implantation into the barrier layer is performed, then doped region formation is achieved, but the doped region depth becomes excessive affecting device resistance and switching operations

Engineering Contradiction:
Improvedoped region depth controlVSAvoiddevice switching operation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A cap layer is formed on the barrier layer before ion implantation. This cap layer serves as a depth control mechanism that prevents ions from penetrating too deeply into the barrier layer and buffer layer, thereby controlling the doped region depth to appropriate levels that maintain device resistance and switching operation characteristics.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If precise control over doped region formation is achieved, then device performance is improved, but the fabrication process complexity increases

Engineering Contradiction:
Improvedoped region formation controlVSAvoidfabrication process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The barrier layer structure is segmented into multiple components: the barrier layer itself and an additional cap layer formed on top. This segmentation allows the ion implantation process to be controlled in stages, with the cap layer acting as a sacrificial depth control element that can be removed later, simplifying the overall control of doped region formation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cap layer serves as an intermediary element between the ion source and the barrier layer. It mediates the ion implantation process by absorbing excess ion penetration and providing a controlled interface for doping, thereby achieving precise doped region formation without requiring complex process control mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables precise control over the doped region, enhancing the switching operation from Normally-on to Normally-off states and maintaining device performance by preventing excessive doped region depth, thus improving the overall efficiency and reliability of HEMTs.

Implementation Method 1

performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS20250015173A1High electron mobility transistor and method for fabricating the same
Publication Date: 2025.01.09 UNITED MICROELECTRONICS CORP
  • US20250015173A1 patent drawing
  • US20250015173A1 patent drawing
  • US20250015173A1 patent drawing

AI summary

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.