GaN HEMT Gate Wiring for Heat Dissipation

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Solution Overview

Problem

In semiconductor devices, particularly multi-finger field effect transistors, there is a trade-off between heat dissipation and chip size, where increasing heat dissipation requires larger chip sizes and decreasing chip size results in reduced heat dissipation, posing a challenge for high-frequency power amplifiers like GaN HEMTs.

Innovation Solution

The semiconductor device design includes a substrate with gate fingers arranged orthogonally and connected via gate connection wiring, where the connection points of gate fingers to the wiring are strategically positioned to enhance heat dissipation, with overlapping bonding wires and alternating source and drain fingers, and a bonding material that spreads heat flow paths, utilizing high thermal conductivity materials like SiC substrates to reduce thermal resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the chip size is increased to improve heat dissipation, then heat dissipation performance is improved, but chip size increases

Engineering Contradiction:
Improveheat dissipationVSAvoidchip size
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The gate connection wiring is divided into multiple segments corresponding to different gate fingers, with each segment connecting to a specific gate finger at a distinct position. This segmentation allows heat from different gate fingers to be dissipated through separate pathways to the side surface, improving overall heat dissipation efficiency without requiring a larger chip area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes the side surface of the substrate as an additional heat dissipation dimension. By extending gate connection wirings to connect gate fingers to the side surface, heat can be dissipated in the vertical dimension rather than only in the planar direction, effectively increasing heat dissipation capability without proportionally increasing chip area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If the gate connection wiring is extended to improve heat dissipation, then heat dissipation is improved, but device complexity increases

Engineering Contradiction:
Improveheat dissipationVSAvoidwiring complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

Different gate fingers are connected to the gate connection wiring at different positions along the wiring, creating local variations in connection points. This local differentiation optimizes heat dissipation for each gate finger while maintaining a relatively simple overall wiring structure, as the variations are localized rather than systematic across the entire device.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves heat dissipation while maintaining or reducing the chip size, thereby enhancing the performance and lifespan of high-frequency power amplifiers by lowering thermal resistance and maintaining efficient FET characteristics.

Implementation Method 1

utilizing high thermal conductivity materials like SiC substrates to reduce thermal resistance

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a bonding material that spreads heat flow paths

Methodology Applied
Scientific EffectHeat spreading: Conduction (thermal)

Data Source

PatentUS20230042301A1Semiconductor device
Publication Date: 2023.02.09 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US20230042301A1 patent drawing
  • US20230042301A1 patent drawing
  • US20230042301A1 patent drawing

AI summary

A semiconductor device includes a substrate, an active region provided in the substrate, a plurality of gate fingers provided on the active region, extending in an extension direction, and arranged in an arrangement direction orthogonal to the extension direction, and a gate connection wiring commonly connected to the plurality of gate fingers and provided between the plurality of gate fingers and a first side surface of the substrate, wherein when viewed from the arrangement direction, a first position where a first end of a first gate finger as a part of the plurality of gate fingers is connected to the gate connection wiring is closer to the first side surface than a second position where a first end of a second gate finger as another part of the plurality of gate fingers is connected to the gate connection wiring.