GaN HEMT Gate-Nested Transistor Structure for Lower On-Resistance
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Solution Overview
Problem
Normally-off high electron mobility transistors based on gallium nitride suffer from high on-state resistance and parasitic capacitive elements, which degrade their performance, especially at high switching frequencies.
Innovation Solution
The design incorporates a second transistor located inside the gate region of the first transistor, with conductive material extending along the sides of the gate region to contact doped regions, and an insulating layer to reduce on-state resistance and parasitic capacitance, allowing for better control of the threshold voltage and improved electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normally-off HEMT transistor with MIS gate is used, then the transistor can maintain an off-state at zero gate voltage, but the on-state resistance becomes strongly increased
Solution Approach 1:
A second transistor is integrated inside the gate region of the first transistor. The second transistor's channel region is formed within the gate region, and its source and drain regions are positioned to create conductive paths that reduce the on-state resistance of the first transistor while maintaining the normally-off capability through the combined structure
Solution Approach 2:
The invention introduces a vertical dimension by forming a trench structure and placing the second transistor inside the gate region of the first transistor. This three-dimensional integration allows the conductive material of the second transistor to extend along the sides of the gate region, creating additional conduction paths that reduce on-state resistance without compromising the normally-off characteristic
2Ease of operation
If the gate region is made larger to improve control, then the threshold voltage control improves, but parasitic capacitive elements increase
Solution Approach 1:
The second transistor is nested within the gate region of the first transistor, utilizing the same spatial volume to provide additional functionality. This integration allows improved threshold voltage control through the second transistor's channel while the conductive material strategically placed along the gate region sides minimizes parasitic capacitance by providing controlled conduction paths
3Object-affected harmful factors
If conductive material is added to reduce on-state resistance, then electron flow improves, but device complexity increases
Solution Approach 1:
The second transistor is merged with the first transistor by integrating it within the gate region. The conductive material of the second transistor is combined with the gate structure, creating a unified device that reduces on-state resistance through the additional conduction paths while maintaining a manageable structural complexity through systematic integration
Data Source
AI summary
A device including a first transistor, having a gate region partially penetrating into a gallium nitride layer, and a second transistor located inside of the gate region of the first transistor.