GaN HEMT Gate Structure Using Shaped P-Type Recesses

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Solution Overview

Problem

Current methods for fabricating high electron mobility transistors (HEMTs) from GaN-based materials face challenges in achieving optimal structural configurations for enhanced performance, particularly in forming p-type semiconductor layers that effectively support gate and field plate structures for improved electrical characteristics.

Innovation Solution

The method involves forming a buffer layer, a barrier layer, and a p-type semiconductor layer with specific recess configurations, such as L-shape or T-shape, on a substrate using epitaxial growth processes like MBE or MOCVD, accompanied by photo-etching and electroplating processes to create source and drain electrodes and a gate structure, which includes a field plate for enhanced voltage sustainability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication methods are used to form p-type semiconductor layers, then the basic device structure is achieved, but the electrical performance and channel control efficiency are insufficient

Engineering Contradiction:
Improveelectrical performanceVSAvoidp-type semiconductor layer configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The p-type semiconductor layer is divided into multiple regions with different configurations (L-shaped, T-shaped, inverted T-shaped) to optimize electrical performance in different areas of the device

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces vertical recesses and multi-level structures in the p-type semiconductor layer, adding dimensional complexity to improve channel control and electrical characteristics

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If the p-type semiconductor layer is formed with complex recess configurations, then channel control and voltage sustainability are improved, but the fabrication process complexity increases

Engineering Contradiction:
Improvechannel control efficiencyVSAvoidfabrication process
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

Recesses are pre-formed in the p-type semiconductor layer before depositing the gate electrode, allowing for optimized electrical performance without requiring complex post-processing steps

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses epitaxial growth and deposition processes to create complex three-dimensional structures, replacing what would otherwise require multiple mechanical machining steps

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of HEMTs with improved electrical performance by optimizing the p-type semiconductor layer configuration, allowing for efficient channel control and increased sustainable voltage, thereby enhancing the device's operational capabilities.

Implementation Method 1

forming a buffer layer on a substrate; forming a barrier layer on the buffer layer

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS12107157B2High electron mobility transistor and method for fabricating the same
Publication Date: 2024.10.01 UNITED MICROELECTRONICS CORP
  • US12107157B2 patent drawing
  • US12107157B2 patent drawing

AI summary

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.