GaN HEMT Cascode with Segmented Gate for Reduced Capacitance

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Solution Overview

Problem

High electron mobility transistors (HEMTs), particularly GaN transistors, have large gate-to-drain and gate-to-source capacitances, limiting their switching speed and efficiency in cascode circuits, and existing solutions with Si MOSFETs and HEMTs suffer from parasitic inductance due to separate dies.

Innovation Solution

Integration of a low-side HEMT with a segmented gate electrode and a high-side HEMT within the same die, along with a resistive element coupled to the source and gate of the high-side HEMT, reduces gate capacitance and parasitic characteristics, enabling faster switching and reduced energy losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a single HEMT is used, then the device can carry large current at high temperatures, but the gate-to-drain and gate-to-source capacitances become relatively large, limiting switching speed

Engineering Contradiction:
Improvecurrent carrying capacityVSAvoidswitching speed
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) that are spatially separated. This segmentation reduces the overlapping electric field between gate and drain/source regions, thereby reducing parasitic capacitances while maintaining the overall gate control function and current carrying capability of the HEMT device.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a cascode circuit with Si MOSFET and HEMT is used, then circuit performance is improved, but parasitic inductance increases due to separate dies

Engineering Contradiction:
Improvecircuit performanceVSAvoidparasitic inductance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The Si MOSFET and GaN HEMT are integrated onto a single semiconductor die, merging two previously separate devices into one unified structure. This integration eliminates the inter-die bonding interfaces and connecting traces that introduce parasitic inductance, while preserving the cascode circuit's improved performance characteristics for high-frequency and high-power applications.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If HEMTs are integrated on the same die, then parasitic characteristics are reduced and switching speed increases, but device complexity increases

Engineering Contradiction:
Improveswitching speedVSAvoidintegration complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The integrated device uses segmented gate electrodes with distinct regions (first gate electrode over first semiconductor region, second gate electrode over second semiconductor region) that can be independently controlled. This segmentation allows for optimized electrical characteristics in different parts of the device while maintaining a unified integrated structure, reducing parasitic effects without requiring overly complex external circuitry.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9929261B2Electronic device including a HEMT with a segmented gate electrode
Publication Date: 2018.03.27 SEMICON COMPONENTS IND LLC
  • US9929261B2 patent drawing
  • US9929261B2 patent drawing
  • US9929261B2 patent drawing

AI summary

An electronic device can include a low-side HEMT including a segmented gate electrode; and a high-side HEMT coupled to the low-side HEMT, wherein the low-side and high voltage HEMTs are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side HEMT; a high-side HEMT coupled to the low-side HEMT; and a resistive element. In an embodiment, the resistive element can be coupled to the source electrode and a gate electrode of the high voltage HEMT, and in another embodiment, the resistive element can be coupled to the source electrode and a drain of the low-side HEMT. A process of forming an electronic device can include forming a channel layer over a substrate; and forming a gate electrode over the channel layer. The gate electrode can be a segmented gate electrode of a HEMT.