Enhancement-mode GaN HEMT on Si Substrate with Stress-Managed Buffer
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Solution Overview
Problem
The challenge lies in growing high-quality, crack-free GaN-based epitaxial material on large-sized Si substrates due to significant lattice and thermal mismatches, leading to tensile stress, warping, and reliability issues in GaN-based high-voltage switching devices.
Innovation Solution
An enhancement-mode AlGaN/GaN heterojunction HEMT device is developed on a Si substrate with a specific layer structure including an AlN nucleation layer, AlGaN transition layers, a low-temperature AlN insertion layer, and an AlGaN/GaN superlattice layer, which reduces cumulative stress and improves crystal quality, along with a passivation protective layer and MIS structure to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN-based epitaxial material is grown on large-sized Si substrate, then production cost is reduced and device scalability is improved, but lattice mismatch and thermal mismatch cause tensile stress, warping, and cracking
Solution Approach 1:
The patent segments the GaN-based epitaxial structure into multiple functional layers including AlN nucleation layer, AlGaN transition layers, AlGaN buffer layer, GaN channel layer, and AlGaN barrier layer. Each layer is optimized to manage stress differently, with the buffer layer specifically designed to accommodate lattice mismatch and reduce tensile stress accumulation, enabling large-sized Si substrate usage without cracking
Solution Approach 2:
The patent changes material composition parameters by introducing AlGaN alloys with varying Al content in transition layers and buffer regions. This compositional gradient allows progressive adaptation from Si substrate lattice constant to GaN layer lattice constant, reducing thermal mismatch stress and preventing warping while maintaining cost-effectiveness of Si substrate processing
2Reliability
If AlGaN/GaN heterojunction structure is optimized for high electron mobility, then device performance is improved, but tensile stress accumulation causes defect formation and reliability degradation
Solution Approach 1:
The patent introduces AlGaN buffer layers and AlN insertion layers as intermediary structures between the Si substrate and the GaN channel layer. These intermediary layers gradually transition the lattice constant and reduce the abrupt mismatch, thereby reducing tensile stress accumulation while maintaining the high electron mobility properties of the AlGaN/GaN heterojunction
Solution Approach 2:
The patent employs composite material structures combining AlN, AlGaN with different Al compositions, and GaN in a layered heterostructure. This composite approach allows each material to contribute its advantageous properties: AlN for stress reduction and nucleation, AlGaN for electron mobility and barrier properties, and GaN for channel conduction, while collectively managing tensile stress
3Reliability
If multiple AlGaN transition layers and buffer layers are added to reduce stress, then crack-free growth is achieved, but device structure complexity and manufacturing process difficulty increase
Solution Approach 1:
The patent segments the buffer region into distinct functional zones (AlN nucleation layer, AlGaN transition layers with decreasing Al content, AlGaN buffer layer) that can be grown sequentially using standard MOCVD processes. This segmentation allows each layer to be optimized independently for stress management while maintaining overall structural integrity and manageable manufacturing complexity
Solution Approach 2:
The patent applies local quality optimization by varying Al content specifically in transition layers and buffer regions where stress management is critical, while maintaining high electron mobility in the GaN channel layer and AlGaN barrier layer. This localized compositional control achieves stress reduction without unnecessarily complicating the entire device structure
4Adaptability or versatility
If GaN-based material is grown on Si substrate to enable CMOS compatibility, then integration with existing semiconductor processes is improved, but defect density increases compared to other substrates
Solution Approach 1:
The patent performs preliminary stress management actions by incorporating AlN nucleation layers and AlGaN buffer layers with graded composition before growing the active GaN device layers. This preliminary structuring prevents defect propagation from the Si substrate interface, enabling CMOS-compatible Si substrate usage while maintaining low defect density in the active device regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, improves film quality, reduces defects, and achieves high threshold voltage, high breakdown voltage, and high current density, making it suitable for high-voltage and high-power electronic devices with improved reproducibility.
Implementation Method 1
AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer
Implementation Method 2
a low temperature AlN insertion layer... reduces cumulative stress
Implementation Method 3
an AlGaN/GaN superlattice layer... improves film quality, reduces defects
Implementation Method 4
passivation protective layer... simplifies the manufacturing process, improves film quality
Data Source
AI summary
An enhancement-mode GaN-based HEMT device on Si substrate and a manufacturing method thereof. The device includes a Si substrate, an AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer, a low temperature AlN insertion layer, an AlGaN main buffer layer, an AlGaN/GaN superlattice layer, an GaN channel layer, and an AlGaN barrier layer. Both sides of a top end of the HEMT device are a source electrode and a drain electrode respectively, and a middle of the top end is a gate electrode. A middle of the AlGaN barrier layer is etched through to form a recess, and a bottom of the recess is connected to the GaN channel layer. A passivation protective layer and a gate dielectric layer are deposited on the bottom of the recess, and the gate electrode is located above the dielectric layer.