GaN HEMT on SOI with AlN Interlayers for Crack-Free Growth
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Solution Overview
Problem
GaN-based high electron mobility transistors (HEMTs) face challenges due to high lattice and thermal mismatch between Si and GaN, leading to tensile stress, cracking, and non-uniform composition/thickness in the layer structure, which compromises device performance and makes them unsuitable for high-voltage applications.
Innovation Solution
A semiconductor device structure comprising a substrate, a group(III)-nitride layer, a metal-group(III)-nitride layer, and a metal nitride layer is developed, with a thick AlN layer and AlGaN layer deposited as a gradient to reduce strain and prevent cracking, using a silicon-on-insulator (SOI) substrate to achieve low structure bowing and improve electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN is grown on bulk Si substrate, then manufacturing cost is reduced and manufacturing yield is improved, but lattice mismatch and thermal mismatch cause tensile stress leading to cracking and high dislocation density
Solution Approach 1:
The patent segments the GaN layer into multiple thin layers with alternating composition (GaN/AlGaN superlattice structure). Each thin layer is below the critical thickness for crack formation, yet collectively they provide the necessary thickness for device operation. This segmentation allows growth on Si substrate without cracking while maintaining manufacturing cost advantages.
Solution Approach 2:
The patent employs composite material structures including GaN/AlGaN superlattices and buffer layers with graded composition. These composite structures accommodate the lattice and thermal mismatch between GaN and Si substrate, reducing tensile stress and preventing cracking while enabling cost-effective Si-based manufacturing.
2Reliability
If superlattices or low-temperature AlN interlayers are incorporated to relieve stress, then cracking is reduced, but multilayers of 2DEG interfaces are created causing device leakage and reduced efficiency
Solution Approach 1:
The patent applies local quality by incorporating AlN interlayers only at specific locations where stress relief is most critical, rather than using extensive superlattice structures throughout. This localized approach provides stress relief while minimizing the creation of 2DEG interfaces that cause leakage, thereby maintaining device efficiency.
Solution Approach 2:
The patent extracts the stress-relief function from the bulk GaN layer by introducing discrete AlN interlayers at strategic positions. This removes the need for widespread superlattice structures, eliminating the harmful 2DEG interfaces while retaining the beneficial stress relief effect.
3Reliability
If superlattices or AlN interlayers are incorporated to relieve stress, then cracking is reduced, but growth time increases reducing time and cost efficiency
Solution Approach 1:
The patent applies partial action by incorporating AlN interlayers at optimized concentrations and positions rather than using full superlattice structures throughout the GaN layer. This partial incorporation provides sufficient stress relief to prevent cracking while significantly reducing the total growth time compared to extensive superlattice approaches.
Solution Approach 2:
The patent changes the growth parameters by using low-temperature AlN interlayers grown at specific thicknesses and positions, rather than growing thick GaN layers with superlattice structures. This parameter optimization reduces overall growth time while maintaining crack-free growth through effective stress management.
4Strength
If thick GaN layers are grown to enable high voltage applications, then device voltage capability is improved, but severe substrate bowing prevents use of thin bulk Si substrates
Solution Approach 1:
The patent segments the thick GaN structure into multiple thin layers separated by AlN interlayers. This segmentation distributes the thermal and lattice mismatch stress throughout the structure, preventing severe substrate bowing that would otherwise occur with thick continuous GaN layers, thereby enabling use of thin Si substrates for high-voltage devices.
Solution Approach 2:
The patent uses composite GaN/AlN layer structures where the AlN interlayers have different thermal and mechanical properties that compensate for the stress induced by thick GaN growth. This composite approach maintains structural integrity and minimizes substrate bowing, enabling high-voltage capability on thin Si substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor device with superior crystalline quality and improved electrical properties, suitable for high-power applications, while reducing production costs and time by up to 70% and 30% respectively, compared to traditional methods.
Implementation Method 1
reduce the strain induced by thermal mismatch between the GaN and SOI layer
Implementation Method 2
the AlN layer may provide a better interface for deposition of the AlGaN layer
Data Source
AI summary
The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.