GaN HEMT Staircase Source Field Plate for Lower Cds
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Solution Overview
Problem
The existing semiconductor device configurations for power amplification using GaN HEMTs suffer from increased parasitic capacitance between the 2DEG surface and the field plate, leading to higher power consumption due to the close proximity of the field plate to the semiconductor layer, which is not effectively addressed by current field plate configurations.
Innovation Solution
A semiconductor device design where the position of the lowermost surface of the source field plate is set to be identical to or above the upper surface of the insulating layer in contact with the gate electrode, and the upper-edge position of the side surface of the source field plate is lower than the uppermost surface of the gate electrode, reducing the parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source field plate is positioned close to the semiconductor layer to relax the electric field between gate and drain electrodes, then electric field relaxation is improved, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The source field plate is positioned at a different vertical height (z-dimension) relative to the gate electrode, specifically at the same height as the upper surface of the insulating layer. This spatial reconfiguration maintains effective electric field relaxation between gate and drain while increasing the vertical distance to the 2DEG surface, thereby reducing parasitic capacitance and power consumption
Solution Approach 2:
The source field plate is designed with asymmetric positioning where its lowermost surface aligns with the insulating layer height rather than being uniformly close to the semiconductor layer throughout. This creates localized electric field relaxation where needed while minimizing parasitic capacitance in the critical region near the 2DEG surface
2Reliability
If the source field plate is positioned to cover the drain-side edge portion of the gate electrode for enhanced electric field relaxation, then electric field relaxation is improved, but parasitic capacitance between the field plate and 2DEG surface increases
Solution Approach 1:
The source field plate utilizes vertical positioning (z-dimension) by aligning its lowermost surface with the insulating layer upper surface, creating effective electric field relaxation in the horizontal plane while maintaining sufficient vertical separation from the 2DEG surface to minimize parasitic capacitance
Solution Approach 2:
The insulating layer serves as an intermediary between the source field plate and the 2DEG surface. By positioning the field plate at the same height as the insulating layer surface, the insulating layer acts as a physical barrier that reduces direct capacitive coupling between the field plate and the conductive 2DEG surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves both electric field relaxation between the gate and drain electrodes while minimizing parasitic capacitance, thereby reducing power consumption and enhancing the gain characteristics for high-frequency applications.
Implementation Method 1
high-speed operating characteristics due to the high mobility of the two-dimensional electron gas (hereafter also referred to as "2DEG: two dimensional electron gas") that is generated in proximity to a heterojunction interface by the piezoelectric effect
Implementation Method 2
the gate electrode forming a Schottky junction with an upper surface of the second nitride semiconductor layer through a first opening provided in the first insulating layer
Data Source
AI summary
A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.