GaN HEMT Carrier Trapping Compensation via Closed-Loop Feedback
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Solution Overview
Problem
Existing approaches for addressing carrier trapping in GaN-based High Electron Mobility Transistors (HEMTs) use open-loop techniques that cannot detect dynamic trap behaviors, leading to non-linear distortion in output signals and long-term memory effects.
Innovation Solution
A closed-loop circuit is introduced, which includes a reference transistor coupled to a power FET, an active bias circuit, and a summing node to detect changes in drain current and generate a compensation signal applied to the gate of the power FET, allowing for real-time correction of gate bias voltage based on trapping behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If open-loop techniques are used to address carrier trapping, then device simplicity is maintained, but non-linear distortion and long-term memory effects occur due to inability to detect dynamic trap behaviors
Solution Approach 1:
The patent implements a closed-loop feedback system that continuously monitors the drain current of the power FET and dynamically adjusts the gate bias voltage to compensate for carrier trapping effects. The feedback circuit detects changes in drain current caused by trapping and generates a compensating signal that is added to the gate bias, thereby maintaining linear output signals and eliminating long-term memory effects.
2Reliability
If a closed-loop circuit is introduced to detect and compensate trapping, then output signal linearity is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent introduces a reference FET that serves as an intermediary device to sense carrier trapping effects. The reference FET is operated in a diode configuration and experiences the same trapping conditions as the power FET. By monitoring the drain current of the reference FET, the system indirectly detects trapping behavior without requiring direct measurement of the power FET's internal state, thus simplifying the overall compensation circuitry.
Solution Approach 2:
The reference FET creates a simplified copy of the power FET's trapping behavior. Instead of directly monitoring the complex power FET, the system uses the reference FET as a surrogate that replicates the trapping effects. This copying approach allows for easier detection and compensation while reducing the complexity of the monitoring circuit.
3Reliability
If real-time compensation is implemented, then long-term memory effects are reduced, but manufacturing complexity increases due to additional fabrication steps
Solution Approach 1:
The patent merges the power FET and reference FET into a single integrated structure fabricated on the same semiconductor substrate. Both devices share common fabrication steps and are formed using the same material layers, which significantly reduces manufacturing complexity. The reference FET is simply an additional structure that can be incorporated into the existing power FET fabrication process without requiring separate manufacturing lines or additional complex steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The closed-loop circuit effectively compensates for carrier trapping effects in HEMTs, reducing non-linear behavior and maintaining constant drain current, as demonstrated by simulation results showing improved performance with and without trapping compensation.
Implementation Method 1
A major portion of the electrons in the 2DEG may be attributed to polarization in the AlGaN
Data Source
AI summary
A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.