Asymmetrical GaN HFET Plug Layout for High-Voltage Interconnects
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Solution Overview
Problem
The existing high voltage heterostructure field effect transistors (HFETs) require multiple stacked tungsten plugs to achieve the necessary thickness for voltage holding, which increases manufacturing costs and complexity, and may compromise reliability due to the additional processing steps.
Innovation Solution
An asymmetrical plug interconnect structure is used, where the interconnect metal is deposited off-center and the plugs are formed above a 'wing' of the interconnect metal, alternating around the center axis, allowing for a single plug to reach the required thickness without the need for stacked plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple stacked tungsten plugs are used to achieve necessary thickness for voltage holding, then the voltage holding capability is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent employs asymmetrical plug structures where plugs are positioned at different locations and orientations around the gate contact, rather than using symmetrical stacked plugs. This asymmetrical arrangement allows a single plug to achieve the necessary thickness for voltage holding while simplifying the manufacturing process by eliminating the need for multiple stacked plugs and associated alignment steps.
Solution Approach 2:
Instead of stacking plugs vertically in one dimension to achieve thickness, the patent distributes plugs across multiple locations and orientations in different spatial dimensions around the gate contact. This dimensional redistribution allows the structure to achieve equivalent or superior voltage holding capability with fewer individual plug formation steps.
2Strength
If multiple stacked tungsten plugs are used to achieve necessary thickness, then the voltage holding capability is improved, but the manufacturing cost increases
Solution Approach 1:
The asymmetrical plug configuration enables cost-effective manufacturing by reducing the number of plugs required from multiple stacked units to a fewer number of strategically positioned plugs. This reduction directly lowers material costs, processing costs, and inspection costs while maintaining the necessary voltage holding performance.
Solution Approach 2:
The patent extracts and eliminates the unnecessary stacked plug structure, retaining only the essential plug elements needed for voltage holding. By removing redundant plugs and their associated formation steps, the manufacturing cost is reduced while the core functionality is preserved.
3Length of stationary object
If multiple stacked plugs are used, then the thickness requirement is met, but the reliability may be compromised due to additional processing steps
Solution Approach 1:
The asymmetrical plug structure improves reliability by reducing the total number of plugs and their formation steps. Fewer plugs mean fewer potential failure points, fewer alignment errors, and reduced cumulative variability in the manufacturing process, thereby enhancing overall device reliability while still achieving the required thickness for voltage holding.
Solution Approach 2:
By distributing plugs across different spatial locations and orientations rather than stacking them vertically, the patent reduces the cumulative effect of processing variations and defects. This dimensional distribution strategy enhances reliability by minimizing the impact of any single plug formation variation on the overall device performance.
Data Source
AI summary
A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.