GaN Semiconductor Isolation via Insulating Substrate
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Solution Overview
Problem
Conventional semiconductor structures with GaN devices face challenges in lateral isolation due to back bias effects, which impact breakdown voltages and electrical characteristics, especially when multiple devices with different bias conditions are integrated on the same substrate.
Innovation Solution
A semiconductor structure utilizing an insulating core substrate with a similar coefficient of thermal expansion to transistor material layers, surrounded by an engineered layer, and featuring a simple isolation structure such as a trench filled with insulating material or separated implant regions to prevent electrical connections between devices, eliminating the need for bias connections and complex conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lateral isolation structure formed by ion-implantation or shallow etching is used to interrupt the 2DEG layer, then device isolation is achieved, but back bias effect is generated from the semiconductor substrate impacting breakdown voltages and electrical characteristics
Solution Approach 1:
The patent extracts the harmful conductive substrate from the system by replacing it with an insulating substrate. This removes the source of back bias effect while maintaining the necessary device isolation function. The insulating substrate is completely non-conductive, eliminating any possibility of back bias generation while still providing electrical isolation between devices.
Solution Approach 2:
The patent introduces an engineered layer as an intermediary between the insulating substrate and the GaN device layers. This engineered layer serves as a mediator that provides a suitable interface for epitaxial growth while maintaining the insulating properties, thus preventing back bias effects while enabling proper device formation and isolation.
2Adaptability or versatility
If multiple devices with different bias conditions are integrated on the same substrate, then circuit integration is achieved, but electrical interference between devices occurs due to substrate conduction
Solution Approach 1:
The patent removes the conductive substrate that causes electrical interference between integrated devices. By using an insulating substrate, each device operates independently without electrical coupling through the substrate, enabling multiple devices with different bias conditions to be integrated without interference while maintaining proper electrical isolation.
3Reliability
If a complex isolation structure with bias connection is used to eliminate back bias effect, then breakdown voltage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the entire complex bias connection infrastructure by using an insulating substrate from the outset. This eliminates the need for deep trenches, conductive fillers, and bias connection pathways, significantly simplifying the device structure while maintaining high breakdown voltage performance through simple lateral isolation.
Solution Approach 2:
The patent replaces expensive complex isolation structures with a simple insulating substrate that inherently provides the necessary isolation function. The insulating substrate is a cost-effective, simple material that eliminates the need for complex processing steps and expensive conductive materials, reducing both manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively isolates GaN devices, eliminating back bias effects and enabling the integration of multiple devices with different voltage applications on the same die without the need for complex substrate connections, thus improving electrical characteristics and reducing manufacturing costs.
Implementation Method 1
The insulating substrate has a coefficient of thermal expansion (CTE) that is similar to the CTE of the first epitaxial layer
Implementation Method 2
The insulating substrate has a thermal conductivity that is higher than that of silicon
Implementation Method 3
The nucleation layer is formed on the engineered layer
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.