Three-Phase GaN Inverter Chip Layout Without Bond Wires
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Solution Overview
Problem
Three-phase inverter bridges using GaN HEMTs face issues with low integration and complex packaging due to excessive bond wires, leading to increased parasitic inductance and reduced circuit efficiency.
Innovation Solution
A method for preparing a three-phase inverter power chip by directly forming six GaN HEMTs on a substrate, where the source, drain, and gate electrodes of the transistors are electrically connected to bond pads instead of bond wires, reducing parasitic inductance and improving integration and packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If six GaN HEMTs are connected by bond wires to form a three-phase inverter bridge, then the circuit can be assembled, but the integration is low and the packaging becomes complex
Solution Approach 1:
The patent merges six separate GaN HEMT chips into a single integrated chip structure. The inverter unit includes six GaN HEMTs formed on the same substrate with their electrodes directly connected through conductive layers, eliminating the need for external bond wires and packaging complexity while achieving full functional integration
2Ease of manufacture
If excessive bond wires are used to connect GaN HEMTs, then the circuit can be assembled, but parasitic inductance increases and circuit efficiency decreases
Solution Approach 1:
The patent extracts and eliminates the bond wires from the circuit assembly process. The GaN HEMTs are directly formed on the substrate with their source, drain, and gate electrodes connected through integrated conductive layers, completely removing the harmful parasitic inductance introduced by external bond wires while maintaining circuit functionality
Data Source
AI summary
The present disclosure relates to a field of chip technology, and discloses a three-phase inverter power chip and a preparation method therefor. The preparation method includes: forming active areas on a substrate and an isolation area located outside the active areas; forming a source electrode, a drain electrode and a gate electrode of a transistor in each active area; forming a first bond pad, second bond pads, third bond pads and fourth bond pads in the isolation area; the source electrode, the drain electrode and the gate electrode of the chip being extended to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto; and electrically connecting the source electrode, the drain electrode and the gate electrode of the transistor to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto.