GaN Vertical JFET Planar Regrowth for Defect Reduction
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Solution Overview
Problem
Conventional power electronics face limitations in creating high-performance vertical GaN-based semiconductor devices due to high defect densities and mismatched substrates, which hinder the development of efficient power electronic devices like JFETs.
Innovation Solution
The method involves forming III-nitride epitaxial layers on pseudo-bulk GaN substrates using homoepitaxial GaN layers, allowing for selective regrowth of planar regions, which improves device yield, current-handling capability, and reliability by minimizing defect density and optimizing dopant concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional substrates are used for GaN-based devices, then manufacturing is simpler, but defect density increases and device reliability deteriorates
Solution Approach 1:
The patent employs homoepitaxial growth where GaN layers are grown on GaN substrates, ensuring material homogeneity between layer and substrate. This eliminates lattice mismatch and thermal expansion differences, thereby reducing defect density and improving device reliability while maintaining manufacturing feasibility through established epitaxial processes.
Solution Approach 2:
The patent changes the substrate material parameter from conventional materials (Si, SiC) to GaN itself, fundamentally altering the interface properties. This parameter change eliminates the harmful effects of lattice mismatch and thermal stress, leading to lower defect densities and improved device performance.
2Manufacturing precision
If selective regrowth is performed to create planar surfaces, then lithography precision improves, but process complexity increases
Solution Approach 1:
The patent performs preliminary planarization through selective epitaxial regrowth before the lithography process. By pre-forming planar surfaces in the recessed regions, subsequent lithography steps can be performed with higher precision without the complications of non-planar substrates, effectively decoupling the planarization and lithography processes.
Solution Approach 2:
The patent introduces an intermediary epitaxial regrowth step that fills recessed regions and creates planar surfaces. This intermediary process acts as a mediator between the rough etched surface and the precision lithography requirement, enabling high-resolution patterning by providing a planar working surface.
3Area of moving object
If recessed regions are formed to enable selective regrowth, then active area is maximized, but manufacturing steps increase
Solution Approach 1:
The patent applies local quality by forming recessed regions only in specific areas where selective regrowth is needed, rather than processing the entire wafer uniformly. This localized approach maximizes the active area for device formation while minimizing the overall process complexity and maintaining manufacturing efficiency through selective rather than universal processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-voltage, low-resistance GaN-based vertical JFETs with improved thermal conductivity and reliability, maximizing active area and current handling while simplifying lithography and packaging processes.
Implementation Method 1
forming a III-nitride epitaxial layer coupled to the III-nitride substrate. The III-nitride epitaxial layer has an upper surface and a thickness. The method also includes removing a predetermined portion of the III-nitride epitaxial layer to form one or more recessed regions extending from the upper surface to a predetermined depth into the III-nitride epitaxial layer and regrowing a III-nitride epitaxial material in the one or more recessed regions
Data Source
AI summary
A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.