Differential GaN Latch Circuit for Common-Mode dv/dt Rejection

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Solution Overview

Problem

Existing latch circuits in half-bridge IC designs, particularly those using GaN technology, face issues with common-mode voltage changes causing corruption of logic values due to fast positive or negative dv/dt at the SW node, and require p-FETs that are not feasible in GaN processes.

Innovation Solution

A cross-coupled differential activated latch circuit with n-FETs and inverters that implement specific logic functions to prevent latch output changes unless digital input values are different, effectively rejecting common-mode voltage and not requiring p-FETs, allowing implementation in GaN technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a cross-coupled latch circuit is used with floating supply voltage, then the latch can operate with fast dv/dt at SW node, but common-mode voltage changes corrupt the logic values stored in the latch

Engineering Contradiction:

Improvedv/dt response speedVSAvoidlogic value integrity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The latch circuit is segmented into differential pairs where each input has its own dedicated transistor (M1, M2 for inputs; M3, M4 for outputs). This segmentation isolates the effect of common-mode voltage changes on each side, preventing them from corrupting the differential logic state. The differential structure allows the circuit to respond to fast dv/dt while maintaining logic integrity through the differential comparison mechanism.

Inventive Principle:

Principle #1Segmentation

2Reliability

If diode-connected FETs are added for protection, then gate voltages are protected from large common-mode voltage, but the circuit requires p-FETs which are not feasible in GaN processes

Engineering Contradiction:

Improvegate voltage protectionVSAvoidGaN process compatibility

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The circuit uses homogeneous n-FETs throughout (M1-M4 are all n-FETs) to achieve GaN process compatibility. The differential pair structure inherently provides protection mechanisms without requiring diode-connected FETs or p-FETs. The symmetry and matching characteristics of the homogeneous n-FET differential pair provide the necessary protection while maintaining compatibility with GaN technology which typically only supports n-FET fabrication.

Inventive Principle:

Principle #33Homogeneity

3Productivity

If differential current is used to pull down latch inputs, then logic changes can be produced, but large currents are required to quickly charge/discharge parasitic capacitances

Engineering Contradiction:

Improvelogic switching speedVSAvoidcurrent consumption

Core Design Contradiction:

ProductivityVSPower

Solution Approach 1:

The circuit employs dynamic operation where transistors M1 and M2 are activated only when differential input changes occur, rather than continuously. The differential pair structure allows the circuit to dynamically respond to input changes while maintaining low static power consumption. The parasitic capacitances C1 and C2 are charged/discharged only during transitions, reducing overall power requirements compared to continuous high-current operation.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11496134B2Differential activated latch for GaN based level shifter

Publication Date: 2022.11.08 EFFICIENT POWER CONVERSION CORP

AI summary

A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.