GaN Layer Annealing After Substrate Removal for Defect Reduction
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Solution Overview
Problem
The growth of gallium nitride (GaN) on silicon substrates often results in defects due to lattice mismatch and thermal expansion differences, leading to power loss and performance issues in semiconductor devices.
Innovation Solution
The proposed solution involves annealing the GaN semiconductor layer with focused energy after it is isolated from the substrate, which reduces defects by softening the layer and fusing defects, thereby improving the layer's ability to handle higher voltage signals without power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GaN is grown on silicon substrate, then semiconductor device can be manufactured, but defects occur due to lattice mismatch and thermal expansion differences
Solution Approach 1:
The patent applies preliminary action by performing annealing treatment on the GaN layer before isolating it from the substrate. This pre-treatment softens the GaN layer and fuses defects while the substrate is still providing support, preventing the layer from breaking apart. The annealing is conducted at temperatures between 500-1500°C to facilitate defect reduction while maintaining structural integrity during the subsequent isolation process.
Solution Approach 2:
The patent uses an intermediary approach by introducing a controlled thermal field as a mediator between the GaN layer and the substrate. The annealing process creates a thermal environment that facilitates defect fusion and layer softening without requiring direct mechanical intervention. This thermal intermediary enables defect reduction while the substrate continues to provide mechanical support during the treatment.
2Reliability
If annealing is performed on GaN layer, then defects are reduced and electrical performance improves, but additional process time is required
Solution Approach 1:
The patent merges the annealing process with the substrate isolation process into a single integrated workflow. The GaN layer is annealed while still supported by the substrate, and then the annealed layer is isolated in the same continuous process flow. This merging eliminates the need for separate annealing and isolation steps, reducing total process time while achieving both defect reduction and layer separation.
Solution Approach 2:
The patent applies parameter changes by optimizing the annealing temperature range (500-1500°C) and controlling the thermal profile to achieve defect reduction in a single treatment step. By carefully selecting and controlling these thermal parameters, the process achieves effective defect fusion and layer softening without requiring multiple sequential treatments, thereby reducing overall process time while maintaining high electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The annealing process significantly reduces defects in the GaN layer, enhancing its breakdown voltage, electrical performance, reliability, and wafer yield, while also allowing for faster subsequent growth operations.
Implementation Method 1
annealing the semiconductor layer with focused energy after the semiconductor layer is isolated from the substrate
Implementation Method 2
annealing the GaN semiconductor layer with focused energy after it is isolated from the substrate, which reduces defects by softening the layer and fusing defects
Implementation Method 3
reduces defects by softening the layer and fusing defects
Data Source
AI summary
Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.