GaN Semiconductor Device Reducing Leakage Current
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Solution Overview
Problem
GaN-based nitride semiconductor devices used in power electronics often exhibit high off-state leakage current due to the interface between active and inactive regions, which is challenging for achieving low on-resistance and efficient power switching.
Innovation Solution
A semiconductor device structure is introduced, featuring a substrate with a first nitride semiconductor layer, a second nitride semiconductor layer with higher bandgap energy, and a P-type GaN layer disposed between the source and drain electrodes, which surrounds at least one of the electrodes, effectively reducing the off-state leakage current by eliminating electron paths through the inactive region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a P-type GaN layer is formed in the gate region to achieve normally off characteristics, then the device can be turned off, but off-state leakage current increases due to the interface between active and inactive regions
Solution Approach 1:
The patent extracts and removes the harmful interface region between active and inactive regions by eliminating the inactive region entirely. The gate structure is designed to extend only over the active region, and the inactive region formation steps (ion implantation or etching) are omitted, thereby removing the leakage path at the interface while preserving the normally off characteristic through the P-type gate layer.
Solution Approach 2:
Instead of forming an inactive region to define boundaries and reduce parasitic capacitance (conventional approach), the patent inverts the approach by extending the gate and P-type layer directly to the device edges without creating an inactive region. This inversion eliminates the harmful interface while achieving boundary definition through the gate structure itself.
2Device complexity
If an inactive region is formed by ion implantation or etching to reduce parasitic capacitance, then parasitic capacitance decreases, but manufacturing complexity and damage to the channel increase
Solution Approach 1:
The patent extracts and removes the inactive region formation steps (ion implantation or etching processes) from the manufacturing sequence. By designing the gate to extend directly to device edges and omitting the inactive region, the complex multi-step processes for creating and modifying inactive regions are eliminated, simplifying manufacturing while achieving acceptable parasitic capacitance through the gate structure design.
Solution Approach 2:
The patent segments the device structure by clearly defining the active region boundaries through the gate extension rather than through a separate inactive region. This segmentation approach eliminates the need for additional processing steps to create inactive regions, as the gate structure itself provides the necessary regional definition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure significantly reduces off-state leakage current and on-resistance, enabling a normally off JFET with improved performance for power switching applications.
Implementation Method 1
piezoelectric polarization occurring at the hetero-interface between the undoped GaN channel layer and the AlGaN barrier layer is offset by piezoelectric polarization occurring at the hetero-interface between the AlGaN barrier layer and the P-type GaN layer
Implementation Method 2
a heterojunction of a nitride semiconductor has a characteristic that spontaneous polarization and piezoelectric polarization produce a high concentration of carriers at the hetero-interface
Data Source
AI summary
A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.