GaN Logic Level Translator With Resistive Hysteresis Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing logic-level shifter circuits fail to reliably translate low-voltage CMOS signals to a level sufficient to turn-on GaN FETs, and are prone to process and temperature variations, leading to inconsistent performance.
Innovation Solution
A GaN-based level-shifter circuit utilizing a resistive network and GaN differential comparator, with voltage dividers and hysteresis circuits to ensure optimal bias points and insensitivity to process and temperature variations, translating CMOS signals to appropriate levels for GaN FET control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic-level shifter circuits are used, then circuit simplicity is maintained, but the circuit fails to reliably translate low-voltage CMOS signals to a level sufficient to turn-on GaN FETs due to threshold voltage variations
Solution Approach 1:
The patent changes the threshold voltage parameter by using a GaN-based FET (third FET) with a lower threshold voltage (1.5-2.5V) compared to conventional CMOS FETs (0.6-0.7V). This parameter change enables the FET to be reliably turned on by CMOS logic level signals (1.4V for 1.8V supply or 2.0V for 3.3V supply) without requiring complex level shifting circuits, thus improving reliability while maintaining circuit simplicity.
2Reliability
If the threshold voltage of FETs is made significantly lower than the supply voltage for proper operation, then circuit operation is ensured, but the circuit becomes sensitive to process and temperature variations causing threshold voltage drift
Solution Approach 1:
The patent utilizes the inherent parameter characteristics of GaN FETs, specifically their lower and more stable threshold voltage (1.5-2.5V) compared to CMOS FETs. This parameter change provides a larger voltage margin between the threshold voltage and the supply voltage, ensuring reliable circuit operation while reducing sensitivity to process and temperature variations that cause threshold voltage drift.
Solution Approach 2:
The patent employs a simple resistor (101) for biasing the gate of the GaN FET, replacing complex biasing circuits. This approach uses a basic, stable component that is less susceptible to process and temperature variations, thereby improving threshold voltage stability while maintaining circuit simplicity.
3Adaptability or versatility
If input voltage levels are kept low for CMOS compatibility, then CMOS controller integration is achieved, but the voltage is insufficient to turn-on GaN FETs with higher threshold voltages
Solution Approach 1:
The patent changes the threshold voltage parameter by selecting a GaN FET with a threshold voltage (1.5-2.5V) that is compatible with CMOS logic level signals. This parameter selection enables direct integration with CMOS controllers (providing 1.4V or 2.0V signals) while ensuring reliable FET turn-on, thus achieving both CMOS compatibility and reliable GaN FET activation without additional level shifting circuitry.
Data Source
AI summary
A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.