GaN Mesa Via Structure for Low-Parasitic Power Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Group III-Nitride semiconductor devices face challenges in achieving improved performance in terms of low on-resistance, high voltage support, and fast switching times, particularly in power electronic and radio frequency applications.
Innovation Solution
A semiconductor device design featuring a composite layer with a mesa structure embedded in an insulating layer, comprising a Group III nitride-based multilayer structure, and conductive vias for electrode connections, which allows for reduced parasitic effects and enhanced electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Group III-Nitride semiconductor devices are used to achieve fast switching times and low on-resistance, then electrical performance is improved, but parasitic effects increase and manufacturing complexity increases
Solution Approach 1:
The device structure is segmented into distinct functional layers: a Group III nitride semiconductor layer containing the active device, an insulating layer embedding the semiconductor layer's sides, and conductive vias for electrical connections. This segmentation isolates the high-performance semiconductor region from parasitic effects while maintaining electrical performance.
Solution Approach 2:
An insulating layer is introduced as an intermediary material between the Group III nitride semiconductor layer and the surrounding environment. This insulating layer reduces parasitic capacitance and electromagnetic interference, thereby decreasing harmful parasitic effects while preserving the fast switching characteristics of the semiconductor device.
2Reliability
If Group III-Nitride semiconductor devices are used to achieve fast switching times and low on-resistance, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The complex device is divided into manageable segments: the Group III nitride semiconductor layer, the insulating layer, and the conductive via structures. Each segment performs a specific function, making the overall complex device easier to manufacture and analyze while maintaining high electrical performance.
Solution Approach 2:
The device employs a composite structure combining Group III nitride semiconductor material with insulating materials and conductive via materials. This composite approach allows each material to contribute its optimal properties: high electron mobility from the nitride semiconductor, parasitic reduction from the insulator, and electrical connection from the conductive vias, thereby managing complexity through functional specialization.
3Object-generated harmful factors
If mesa structure with insulating layer is used to reduce parasitics, then harmful factors are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The insulating layer is formed and applied to embed the sides of the Group III nitride semiconductor layer before subsequent processing steps. This preliminary action establishes the parasitic-reducing structure early in the manufacturing process, simplifying later steps and reducing the precision requirements for subsequent operations.
Solution Approach 2:
The insulating layer is applied locally to embed only the side faces of the mesa structure, rather than uniformly covering the entire device. This localized application reduces parasitic effects at critical interfaces while minimizing the manufacturing precision requirements to only the necessary embedding regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the electrical and thermal performance of Group III nitride devices by minimizing parasitics and enabling flexible fine-pitch processing, supporting high electron mobility and efficient integration with other semiconductor technologies.
Implementation Method 1
the Group III nitride-based multilayer structure is epitaxially formed on the upper surface of the base substrate
Data Source
AI summary
A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.