GaN Lateral-Conduction Metal Bus Layout for High-Current Reliability
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Solution Overview
Problem
The current rating of lateral GaN power devices is limited by the capability of metallizations to drive high currents due to electromigration and self-heating, which is detrimental to the specific on-resistance and requires complex embedded systems and packaging processes.
Innovation Solution
The solution involves properly shaping on-die metallizations with variable width metal buses that follow the current density gradient, using trapezoidal-shaped subregions and optimizing the geometry to minimize area usage and prevent electromigration, without affecting the specific on-resistance of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interdigitated metallization structures are used to carry high currents, then the current rating can be increased, but the die area occupied by pads and metal interconnections increases significantly
Solution Approach 1:
The patent transitions from planar 2D metallization to 3D vertically stacked metallization layers. Multiple metal layers are stacked above each other to form current paths, allowing high current carrying capacity without increasing the planar die area. The vertical stacking enables current to flow through the third dimension (Z-axis) rather than requiring large lateral metal traces.
Solution Approach 2:
The patent implements nested metallization structures where multiple metal layers are stacked and interconnected through vias. The metal layers are arranged in a nested configuration where each layer is contained within the vertical space above the substrate, with lower layers supporting upper layers. This nested arrangement maximizes current carrying capacity within the available vertical space without lateral expansion.
2Reliability
If thick metallizations are used to avoid electromigration, then the current capability is improved, but the device complexity and manufacturing complexity increase due to required post-processing
Solution Approach 1:
The patent performs preliminary action by forming the complete multi-layer metallization structure during the standard CMOS fabrication process before any packaging or post-processing steps. All metal layers and vias are created in-situ during chip manufacturing, eliminating the need for subsequent thick-metal deposition, electroplating, or other complex post-processing operations that would be required for conventional approaches.
Solution Approach 2:
The patent makes the device self-sufficient by integrating all necessary current-carrying metallization structures directly into the chip during fabrication. The device does not require external packaging modifications, attached heat sinks with integrated metallization, or other auxiliary structures to achieve high current capability. The complete current path is contained within the chip itself through the stacked metal layers.
3Reliability
If large metal interconnections are used to reduce electromigration, then the current rating is improved, but the specific on-resistance increases due to larger die area
Solution Approach 1:
The patent reduces specific on-resistance by utilizing vertical current paths through stacked metal layers instead of lateral current paths. The current flows vertically through multiple thin metal layers separated by dielectric, creating a compact current path that minimizes the resistance-area product. This vertical conduction path achieves low specific on-resistance without requiring large lateral metal dimensions that would increase die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the safe carrying of high currents (>10 A) within integrated devices without increasing on-resistance, reducing the need for complex post-processing and packaging, and maintaining low-cost, low-complexity manufacturing.
Implementation Method 1
The current rating of lateral GaN power devices is limited by the capability of metallizations to drive high currents due to electromigration and self-heating
Implementation Method 2
The current rating of lateral GaN power devices is limited by the capability of metallizations to drive high currents due to electromigration and self-heating
Data Source
AI summary
An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.