GaN Transistor Metallization Layout for Lower Output Capacitance
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Solution Overview
Problem
Existing Group III nitride transistor devices face challenges in reducing switching losses due to high output capacitance, which is not effectively addressed by current metallization structures.
Innovation Solution
The proposed Group III nitride transistor device incorporates a metallization structure with a reduced area of overlap between the source and drain fingers and the corresponding buses, achieved by modifying the shape and size of the fingers and buses, thereby reducing the output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the area of overlap between source/drain fingers and buses is reduced to decrease output capacitance, then switching losses are reduced, but on-state resistance may increase
Solution Approach 1:
The patent applies local quality by creating different overlap configurations for source and drain regions. Specifically, the source finger has a first overlap area with the source bus and a second overlap area with the drain bus, while the drain finger has a third overlap area with the drain bus and a fourth overlap area with the source bus. The patent optimizes these local overlap areas differently - reducing the overlap between source finger and drain bus, and between drain finger and source bus, to minimize output capacitance and switching losses while maintaining adequate overlap for low on-state resistance
Solution Approach 2:
The patent resolves the contradiction by transitioning from a single-plane metallization structure to a multi-layer three-dimensional structure. The source and drain buses are arranged in different vertical layers, allowing the fingers to have selective overlap with buses in different dimensions. This spatial separation in the vertical dimension enables reduced capacitive coupling while maintaining electrical connectivity, thus reducing switching losses without significantly increasing on-state resistance
2Reliability
If the metallization structure uses extensive overlap between buses and fingers to ensure low on-state resistance, then electrical connectivity is improved, but output capacitance increases leading to higher switching losses
Solution Approach 1:
The patent applies segmentation by dividing the metallization structure into distinct functional zones with different overlap characteristics. The source finger is segmented into regions with different overlap areas with source and drain buses, and similarly for the drain finger. This segmentation allows different portions to serve different functions: some areas provide low-resistance connectivity while others minimize capacitive coupling, thus resolving the contradiction between electrical connectivity and switching losses
Solution Approach 2:
The patent uses vertical layering to separate the source and drain buses into different planes. This dimensional separation allows the fingers to maintain adequate overlap with their respective buses for low on-state resistance while minimizing parasitic overlap with opposite polarity buses. The three-dimensional arrangement reduces the effective overlap area contributing to output capacitance while preserving essential electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in reduced switching losses by minimizing the output capacitance, while maintaining low on-state resistance, thus enhancing the overall performance of the transistor device.
Implementation Method 1
a Group III nitride channel layer and a Group III nitride barrier layer arranged on the Group III nitride channel layer and forming a heterojunction therebetween
Implementation Method 2
The Group III nitride transistor device may further comprise a gate and be a lateral device with the source, drain and gate arranged on the first major surface. In each transistor cell of the Group III nitride transistor device, the gate is laterally arranged between the source and the drain
Implementation Method 3
The Group III nitride transistor device has reduced switching losses since the output capacitance, CDS, is reduced the output capacitance CDS by the metallization structure having a smaller area of overlap between the drain finger and the source bus than the area of overlap between that drain finger and the drain bus
Implementation Method 4
The source bus overlaps, i.e. extends over and covers part of the source fingers and drain fingers, and the drain bus overlaps, i.e. extends over and covers part of the source fingers and drain fingers. The second conductive layer is arranged on the first major surface above the first conductive layer such that the source bus is arranged above and extends over the source fingers and drain fingers, whereby the source bus is electrically connected to the source fingers and is electrically insulated from the drain fingers
Data Source
AI summary
A Group III nitride transistor device includes: a Group III nitride substrate having a first major surface, a Group III nitride channel layer, and a Group III nitride barrier layer arranged on the Group III nitride channel layer and forming a heterojunction therebetween; transistor cells; and a metallization structure including first and second electrically conductive layers. The first electrically conductive layer includes for each transistor cell a source finger and a drain finger arranged on the first major surface. The second electrically conductive layer includes a source bus and a drain bus. The source bus extends between and electrically connects the source fingers of the transistor cells and extends over and is electrically insulated from the drain fingers. The drain bus extends between and electrically connects the drain fingers of the transistor cells and extends over and is electrically insulated from the source fingers.