GaN Transistor Metallization Layout for Lower Switching Loss
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Solution Overview
Problem
Existing Group III nitride transistor devices face challenges in reducing switching losses due to high output capacitance, which is not effectively addressed by current metallization structures.
Innovation Solution
The proposed Group III nitride transistor device incorporates a metallization structure with a reduced area of overlap between the drain finger and the source bus, and between the source finger and the drain bus, achieved by modifying the shape and size of the source and drain fingers and buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the area of overlap between source finger and drain bus is reduced, then output capacitance is reduced, but on-state resistance may increase
Solution Approach 1:
The source finger and drain bus are designed with non-uniform width profiles along their lengths. The source finger has a wider section under the source bus and a narrower section under the drain bus, while the drain bus has corresponding width variations. This local quality variation reduces the overlap area between source finger and drain bus (lowering output capacitance and switching losses) while maintaining adequate overlap between drain finger and source bus (preserving low on-state resistance).
Solution Approach 2:
The metallization structure employs asymmetric design where the source finger and drain bus have different width profiles compared to the drain finger and source bus configuration. The source finger width varies along its length with specific sections being wider or narrower depending on the underlying bus, creating an asymmetric overlap pattern that optimizes the trade-off between output capacitance and on-state resistance.
2Loss of energy
If the area of overlap between drain finger and source bus is reduced, then output capacitance is reduced, but on-state resistance may increase
Solution Approach 1:
The drain finger is designed with non-uniform width along its length, having a wider section under the drain bus and a narrower section under the source bus. The source bus also has corresponding width variations. This local quality adjustment reduces the overlap area between drain finger and source bus (reducing output capacitance and switching losses) while maintaining adequate electrical contact for low on-state resistance.
Solution Approach 2:
The asymmetric width profiling of drain finger and source bus creates different overlap characteristics compared to the source-finger/drain-bus pair. This asymmetric design allows independent optimization of the two overlap regions to achieve the desired balance between output capacitance reduction and on-state resistance maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the output capacitance and switching losses, while maintaining low on-state resistance, thereby enhancing the overall performance of the transistor device.
Implementation Method 1
a Group III nitride channel layer and a Group III nitride barrier layer arranged on the Group III nitride channel layer and forming a heterojunction therebetween
Data Source
Figure 1
Figure 2A~2D
Figure 2E
AI summary
According to an embodiment, a Group III nitride transistor device is provided that comprises a Group III nitride substrate comprising first major surface, a Group III nitride channel layer and a Group III nitride barrier layer arranged on the Group III nitride channel layer and forming a heterojunction therebetween, a plurality of transistor cells and a metallization structure comprising a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer comprises for each transistor cell a source finger and a drain finger arranged on the first major surface, and the second electrically conductive layer comprises a source bus and a drain bus. The source bus extends between and electrically connects the source fingers of the plurality of transistor cells and extends over and is electrically insulated from the drain fingers. The drain bus extends between and electrically connects the drain fingers of the plurality of transistor cells and extends over and is electrically insulated from the source fingers. In at least one of the transistor cells an area of overlap between the source finger and the source bus is greater than an area of overlap between the same source finger and the drain bus and/or in at least one of the transistor cells an area of overlap between the drain finger and the drain bus is greater than an area of overlap between the same drain finger and the source bus.