GaN Vertical MIS-FET Zigzag Channel Area Efficiency
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Solution Overview
Problem
Current semiconductor devices using GaN materials face challenges in improving area efficiency and stability of characteristics due to limitations in channel and gate electrode configurations, particularly in vertical MIS-FET structures, which affect current capacity and chip size.
Innovation Solution
The semiconductor device employs a zigzag configuration for the channel and gate electrodes with regular bending intervals and angles, utilizing a single equivalent crystal plane orientation to enhance area efficiency and stability, thereby increasing channel width and reducing chip size while maintaining stable threshold voltage and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a straight channel configuration is used, then the device structure is simple, but the channel width and area efficiency are limited
Solution Approach 1:
The channel and gate electrode are configured in a zigzag pattern with regular bending intervals and angles, transforming the straight linear structure into a curved meandering structure. This curvature increases the effective channel width by 1.2 times compared to straight configurations while maintaining manufacturing feasibility through standardized bending patterns.
Solution Approach 2:
The channel extends not only in the vertical stacking direction but also in the lateral plane with zigzag bends. This dimensional expansion from 1D straight line to 2D meandering path increases the channel width and area efficiency without adding vertical complexity to the device stacking structure.
2Area of stationary object
If the chip size is reduced, then the area efficiency improves, but the channel width may be compromised
Solution Approach 1:
The zigzag configuration allows the channel to pack more length within a smaller footprint by utilizing lateral bends. This enables maintaining adequate channel width (increased by 1.2 times) while reducing the overall chip size through more efficient space utilization.
Solution Approach 2:
By extending the channel in the lateral plane through zigzag bends rather than only in the vertical direction, the design achieves increased channel width within a reduced chip footprint, effectively trading vertical space for lateral efficiency.
3Productivity
If the channel and gate electrode are bent in zigzag, then the area efficiency and channel width increase, but the manufacturing complexity increases
Solution Approach 1:
The zigzag pattern uses regular, periodic bends at standardized intervals and angles, transforming a potentially complex irregular curve into a manufacturable repeating pattern. This regularity simplifies photolithography mask design and fabrication while achieving 1.2 times channel width increase.
Solution Approach 2:
The channel and gate electrode are divided into repeating zigzag segments with regular intervals. This segmentation into standardized units simplifies the fabrication process by allowing modular manufacturing and reduces the complexity of defining arbitrary curved paths.
4Reliability
If a single equivalent crystal plane orientation is used, then the threshold voltage and on-resistance stability improve, but the design flexibility is reduced
Solution Approach 1:
The channel and gate electrode are designed with uniform zigzag bends at regular intervals and angles throughout the structure, creating homogeneous electrical characteristics. This homogeneity, combined with single crystal plane orientation, stabilizes threshold voltage and on-resistance by eliminating variations from irregular geometries.
Data Source
AI summary
A semiconductor device of an embodiment includes: a first nitride semiconductor layer of a first conductive type; a second nitride semiconductor layer which is the first conductive type and is provided on the first nitride semiconductor layer; a third nitride semiconductor layer which is a second conductive type and is provided on the second nitride semiconductor layer; a fourth nitride semiconductor layer which is the first conductive type and is provided on the third nitride semiconductor layer; and a first electrode provided in a trench provided in the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer, via a first insulating film.