GaN Monolithic Device Structure for Parasitic Inductance Reduction
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Solution Overview
Problem
Conventional GaN semiconductor devices face challenges with parasitic inductance in power loops, back-gating effects, and insufficient avalanche capability, limiting their integration and performance in high-frequency power applications.
Innovation Solution
A semiconductor device structure with a substrate layer, epitaxial layers of opposing conductivity types, transition, channel, and barrier layers, along with a substrate contact, is designed to reduce parasitic inductance and enhance avalanche capability by configuring the junctions to manage voltage and current during switching events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GaN devices are switched at high speed to increase operation frequency, then productivity is improved, but parasitic inductance generates high voltage spikes that worsen reliability
Solution Approach 1:
The patent merges the high-side and low-side devices into a single monolithic integrated device structure, where the substrate serves as a common reference for both devices. This integration reduces the parasitic inductance in the power loop by eliminating external connections and minimizing current path length, thereby allowing high-speed switching without generating harmful voltage spikes.
Solution Approach 2:
The patent transitions from a planar configuration to a vertical three-dimensional structure by stacking the first and second devices with their respective source and drain regions in different vertical layers. This vertical arrangement shortens the current path and reduces parasitic inductance, enabling high-frequency operation while maintaining reliability.
2Device complexity
If substrate is connected to source of low-side device to enable monolithic integration, then device integration is improved, but back-gating effect worsens for the high-side device
Solution Approach 1:
The patent applies different conductivity types to different regions: the first device has a first conductivity type with its source connected to the substrate, while the second device has a second conductivity type (opposite to the first) with its source connected to the drain of the first device. This local differentiation allows the substrate to serve as a common reference without creating back-gating effects, as each device operates with optimally doped regions for its specific function.
Solution Approach 2:
The patent employs a composite structure with alternating layers of different conductivity types (n-type and p-type GaN) stacked vertically. This composite arrangement enables both devices to be integrated on the same substrate while each device's source is properly referenced, eliminating the back-gating problem through the alternating polarity design.
3Ease of manufacture
If traditional GaN device structure is used, then manufacturing simplicity is maintained, but avalanche capability is insufficient for power switching applications
Solution Approach 1:
The patent uses a composite multi-layer structure with alternating n-type and p-type GaN layers, where each layer is designed with specific thickness and doping concentration. This composite design provides both the mechanical strength needed for power handling and the electrical characteristics for avalanche capability, while remaining compatible with existing GaN fabrication processes.
Solution Approach 2:
The patent optimizes critical parameters including the thickness of each GaN layer, the doping concentration of n-type and p-type regions, and the breakdown voltage characteristics. By carefully controlling these parameters, the device achieves sufficient avalanche capability to withstand power switching stresses while maintaining compatibility with standard GaN manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed device structure effectively reduces parasitic inductance and back-gating issues, enabling reliable high-frequency operation and improved avalanche event handling, thus enhancing the performance and integration of GaN devices in power conversion circuits.
Implementation Method 1
forming a III-nitride heterojunction over a silicon substrate
Implementation Method 2
the parasitic inductance in the power loop
Implementation Method 3
the GaN devices can be switched at a faster speed than traditional silicon-based semiconductor devices
Implementation Method 4
the semiconductor devices are often required to have the capability to withstand the avalanche events
Data Source
AI summary
A semiconductor apparatus includes a plurality of semiconductor devices with a single substrate, a plurality of trench regions, each trench region including a trench, wherein the single substrate includes a substrate layer, a first epitaxial layer of a first conductivity type, disposed on the substrate layer, and a second epitaxial layer of a second conductivity type, disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends through the second epitaxial layer and into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices.