GaN MOS HEMT Gate Drive for Adjustable Switching Timing
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Solution Overview
Problem
Existing semiconductor devices face challenges in adjusting the turn-on and turn-off times of high-speed switching elements, which is necessary for minimizing parasitic inductance effects and optimizing switching losses.
Innovation Solution
The semiconductor device incorporates a first drive circuit and a second drive circuit, each comprising multiple transistors connected in parallel, to adjust the gate charge and discharge currents, thereby controlling the turn-on and turn-off times of the output stage element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the output stage element and drive circuit are formed in the same chip to suppress parasitic inductance effects, then the harmful factors are reduced, but the ability to adjust turn-on and turn-off times is limited
Solution Approach 1:
The drive circuit is segmented into multiple parallel transistor branches (first drive transistor, second drive transistor, third drive transistor) with different gate capacitances. This segmentation allows independent control of charge and discharge paths, enabling adjustable turn-on and turn-off times while maintaining integration on the same chip to suppress parasitic inductance.
Solution Approach 2:
The circuit uses dynamic control through selective switching of different transistor branches based on operational requirements. By dynamically selecting which parallel branches are active during charging and discharging phases, the circuit adapts turn-on and turn-off times to different operating conditions while remaining integrated.
2Loss of energy
If fast switching is implemented to reduce switching losses, then energy efficiency is improved, but parasitic inductance effects and surge voltages increase
Solution Approach 1:
The circuit employs periodic control of gate charging and discharging through separate drive circuits. By controlling the timing and current profiles of gate charge and discharge phases, the circuit achieves fast switching while managing the rate of change to reduce voltage spikes and parasitic effects.
Solution Approach 2:
The circuit changes the gate voltage application parameters by using different current levels and timing for charging versus discharging. The parallel transistor structure allows different effective resistances and charge rates, enabling optimization of switching speed while controlling surge voltages and parasitic inductance effects through parameter adjustment.
Data Source
AI summary
A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.