GaN-MOSFET Switching Stage Using Mid-Node Gate Energy
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Solution Overview
Problem
Conventional Switched Mode Power Supplies (SMPS) face issues with Electromagnetic Interference (EMI) and inefficiencies due to parasitic capacitance dissipation during MOSFET switching, particularly in GaN-based systems, and the need for transformers and current-sensing resistors, which increase size and cost.
Innovation Solution
A switching stage design incorporating a GaN transistor connected in series with a MOSFET, utilizing a low-ohmic path between the mid-node and gate terminal, facilitated by switch circuitry, and a voltage regulator to harness energy from the mid-node for efficient gate-source capacitance charging, eliminating the need for transformers and current-sensing resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional controller IC is used to drive the gate terminal of the MOSFET, then the circuit is simple to implement, but it generates Electromagnetic Interference (EMI) and dissipates energy due to parasitic capacitance
Solution Approach 1:
The patent extracts the problematic conventional controller IC from the circuit and replaces it with a custom gate driver circuit composed of discrete components (resistors, capacitors, transistors). This extraction allows elimination of the EMI-generating elements while maintaining the gate driving function through a carefully designed RC network and transistor switching arrangement that controls the MOSFET gate without producing harmful electromagnetic interference.
Solution Approach 2:
The patent converts the harmful parasitic capacitance effects into a beneficial timing mechanism. By intentionally designing RC time constants that exploit the capacitive effects, the circuit achieves proper gate charging/discharging sequences and dead-time control. The parasitic capacitance that normally causes EMI and energy loss is transformed into a useful timing element that controls the switching sequence and reduces harmful effects.
2Reliability
If a transformer is used in the Boost PFC converter, then it provides isolation and power supply to the controller IC, but it increases the overall size and weight of the converter
Solution Approach 1:
The patent extracts and removes the transformer from the Boost PFC converter circuit. The isolation function is replaced by the inherent galvanic isolation provided by the optocoupler in the feedback circuit, while the controller power supply is derived directly from the rectified input voltage through a simple RC network, eliminating the need for transformer-based isolation and significantly reducing size and weight.
Solution Approach 2:
The patent makes the input voltage serve multiple functions simultaneously. The rectified input voltage provides both the power supply for the controller IC and the isolation barrier, replacing the dual-function role previously performed by the transformer (isolation plus power supply). This multi-functionality approach eliminates the need for a separate transformer component.
3Measurement precision
If a current-sensing resistor is used to measure the current, then the feedback loop can adjust the duty cycle, but it increases power losses and reduces efficiency
Solution Approach 1:
The patent converts the voltage drop across the sensing resistor, which normally represents power loss, into a useful signal. By using the voltage developed across a small sensing resistor in conjunction with a high-impedance operational amplifier circuit, the system achieves accurate current measurement while minimizing power dissipation. The op-amp buffers the sensing resistor, preventing additional loading and maintaining measurement accuracy while keeping losses minimal.
4Productivity
If the gate resistor is adjusted for proper switching, then efficient switching is achieved, but it affects the overall performance and reliability of the PFC circuit
Solution Approach 1:
The patent replaces the static gate resistor with a dynamic switching network that changes the effective gate resistance during different phases of the switching cycle. During turn-on, a low resistance path is provided for rapid gate charging, and during turn-off, a different resistance path is activated for controlled discharge. This dynamic adjustment optimizes both switching speed and reliability without requiring compromise in the gate resistor value.
Solution Approach 2:
The patent implements preliminary charging of the MOSFET gate capacitance through a dedicated RC network before the main switching action. This preliminary action ensures that the gate is properly prepared for switching, reducing the risk of improper switching conditions that could affect reliability. The circuit proactively manages gate voltage levels rather than relying solely on the gate resistor during the switching event.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances power density, reduces EMI, and improves efficiency by optimizing energy usage and minimizing hardware costs, while maintaining reliable and swift MOSFET switching.
Implementation Method 1
parasitic capacitance at the switching node of the SMPS, which is typically dissipated in the channels of the switching element during MOSFET turn-on
Implementation Method 2
utilizing a low-ohmic path between the mid-node and gate terminal, facilitated by switch circuitry, and a voltage regulator to harness energy from the mid-node for efficient gate-source capacitance charging
Data Source
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AI summary
A switching stage of a Switched Mode Power Supply, SMPS, said switching stage comprising a switching element comprising a GaN transistor connected in series with a Metal-Oxide-Semiconductor, MOS, Field Effect Transistor, FET, thereby defining a mid-node in between said GaN transistor and said MOSFET, a controller arranged for driving a gate terminal of said MOSFET based on an Pulse Width Modulation, PWM, input signal, wherein said controller comprises first switch circuitry arranged for providing a low ohmic path between said mid-node and said gate terminal of said MOSFET and control circuitry arranged for controlling said switch circuitry based on said PWM input signal.