GaN Vertical MOSFET P-Type Profile for Threshold and Mobility Control
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Solution Overview
Problem
The formation of a highly concentrated P-type region in GaN-based vertical MOSFETs leads to unintentional diffusion of impurities to the surface during heat treatment, affecting the transistor's characteristics such as increased threshold voltage and reduced mobility.
Innovation Solution
A nitride semiconductor device with P-type impurity regions having a specific concentration profile, including a peak position away from the interface with the gate insulating film, and an inflection point to control impurity diffusion, combined with inert element implantation and controlled heat treatment to maintain optimal impurity concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is performed to activate P-type impurities after ion implantation, then the P-type impurities are activated and the impurity region is formed, but the P-type impurities diffuse from the deep position to the front surface side, causing unintentional concentration increase at the surface
Solution Approach 1:
The patent applies local quality by creating different concentration regions within the impurity region. The impurity region has a first region with lower P-type impurity concentration and a second region with higher concentration, allowing the deep region to maintain high concentration while the surface region has controlled, lower concentration to prevent threshold voltage deterioration.
Solution Approach 2:
The patent uses preliminary action by performing ion implantation to create the desired concentration profile before heat treatment. The ion implantation is designed to place P-type impurities at specific depths, and the subsequent heat treatment activates these impurities in-situ, preventing diffusion to the surface that would occur with conventional methods.
2Strength
If P-type impurities are ion-implanted to form a highly concentrated P+-type region at deep position, then the breakdown voltage is increased, but the concentration control becomes difficult due to diffusion during heat treatment
Solution Approach 1:
The patent divides the impurity region into multiple zones with different concentration levels. The second region at deeper positions has high P-type impurity concentration to ensure high breakdown voltage, while the first region at shallower positions has lower concentration to prevent surface effects and threshold voltage deterioration.
Solution Approach 2:
The patent changes the concentration parameter of P-type impurities as a function of depth. By controlling the ion implantation conditions and heat treatment parameters, the patent achieves a concentration profile where concentration decreases from the deep second region to the shallower first region, simultaneously achieving high breakdown voltage and precise concentration control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents deterioration of transistor characteristics by maintaining threshold voltage and mobility within desired ranges, ensuring high breakdown voltage and reliable device performance.
Implementation Method 1
a step of ion-implanting P-type impurities into a preset region in a gallium nitride layer from a first principal surface side of the gallium nitride layer
Implementation Method 2
a step of, by subjecting the gallium nitride layer into which the P-type impurities and the inert element are ion-implanted to heat treatment and activating the P-type impurities, forming an impurity region of P-type in the gallium nitride layer
Implementation Method 3
By the heat treatment, some of the P-type impurities diffuse from the deep position in the GaN layer to the front surface side
Data Source
AI summary
An impurity region of P-type that the field effect transistor of the nitride semiconductor device includes has a peak position at which concentration of P-type impurities reaches a maximum at a position located away from an interface with a gate insulating film. The impurity region has an inflection point at which concentration of the P-type impurities changes from increase to decrease toward the interface or a rate of decrease in the concentration of the P-type impurities increases toward the interface at a position located between the interface and the peak position.