GaN Nanowire Electronics Defect Reduction via Selective Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Gallium nitride (GaN) semiconductor devices face limitations due to high costs and inferior material quality and high voltage reliability issues stemming from the use of foreign substrates, which result in high defect densities and wafer production costs, particularly due to misfit dislocations and the need for thick buffer layers.
Innovation Solution
A method involving selective area growth of nitride semiconductor nanowires using a continuous metal-organic chemical vapor deposition (MOCVD) process with a low V/III-ratio, where nanowires with consistent crystal structure are grown, and a planarization step forms discreet base elements with insulating properties, reducing dislocation densities and enhancing crystal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional heteroepitaxial growth methods are used on foreign substrates, then production costs are reduced and manufacturing is simplified, but defect density increases and material quality deteriorates
Solution Approach 1:
The patent segments the continuous epitaxial growth process into two distinct phases: nanowire growth phase with low V/III ratio followed by planar growth phase with high V/III ratio. This segmentation allows each phase to be optimized independently, achieving low defect density in nanowires while maintaining manufacturing simplicity through automated phase transition.
Solution Approach 2:
The patent dynamically changes the V/III ratio parameter during the growth process - using low V/III ratio (50-500) during nanowire growth to minimize defects, then transitioning to high V/III ratio (1000-10000) during planar growth for quality film formation. This parameter optimization resolves the contradiction between material quality and manufacturing ease.
2Reliability
If thick buffer layers are added to reduce dislocation density, then device reliability improves, but production cost increases and wafer bow is induced
Solution Approach 1:
The patent extracts and eliminates the need for thick buffer layers by using nanowire-based growth. The nanowires themselves serve as the foundation for low-defect film growth, removing the buffer layer component entirely and thereby reducing device complexity and preventing wafer bow while maintaining high reliability.
Solution Approach 2:
The patent introduces nanowires as an intermediary structure between the substrate and the final device layer. These nanowires act as mediators that reduce dislocation density without requiring thick buffer layers, thus improving reliability while avoiding the complexity and wafer bow issues associated with traditional buffer layer approaches.
3Manufacturing precision
If high precursor flow rates are used during MOCVD growth, then film quality improves, but defect density increases
Solution Approach 1:
The patent employs periodic action by alternating between two growth modes: first growing nanowires under low precursor flow conditions to minimize defects, then switching to high precursor flow conditions for planar film growth to ensure quality. This periodic switching resolves the contradiction between film quality and defect density.
Solution Approach 2:
The patent performs preliminary nanowire growth under optimized low-defect conditions before proceeding to the main film growth. This preliminary action creates a defect-minimized foundation that allows subsequent high-quality film deposition without introducing excessive defects, thereby resolving the quality-defect density contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with significantly reduced defect densities, improved crystal quality, and increased reliability, enabling higher operating voltage and better RF properties, while also reducing production costs by minimizing the need for thick buffer layers and wafer bow.
Implementation Method 1
forming a plurality of semiconductor nanowires over a substrate by a chemical vapor deposition process
Implementation Method 2
planarizing each volume element to form a plurality of discreet base elements having a substantially planar upper surface
Data Source
AI summary
GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.