GaN Power Converter Package Layout for Low-Parasitic Switching
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Solution Overview
Problem
The adverse effects of parasitic inductors in power converter circuits, such as ringing during switching processes, reduce system efficiency and increase Electromagnetic Interference (EMI), especially in high-frequency applications like Buck converters using GaN transistors.
Innovation Solution
The integration of GaN transistor dies and a control circuit on the same bottom structure within an integrated circuit package, where the power switching devices and control circuit connect through conductors in the bottom structure, effectively reduces parasitic effects by minimizing wire length and maximizing contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional discrete component layout is used in power converter circuits, then ease of manufacture is improved, but parasitic inductance increases causing ringing and reduced system efficiency
Solution Approach 1:
The patent combines multiple power switching devices (GaN transistors) and control circuits into a single integrated circuit package, merging previously discrete components into one unified structure. This integration eliminates the need for separate component mounting and interconnections, thereby reducing parasitic inductance and improving system efficiency while maintaining ease of manufacture through standardized packaging.
Solution Approach 2:
The patent implements a nested structure where power switching devices and control circuits are housed within an integrated circuit package. The GaN transistor dies are mounted on an insulating substrate, which is then enclosed in a protective package with optimized internal routing. This nested arrangement minimizes wire length and contact area for parasitic effects while preserving manufacturing simplicity.
2Loss of energy
If wire length is reduced to minimize parasitic effects, then system efficiency improves, but manufacturing complexity increases
Solution Approach 1:
By merging power switching devices and control circuits into a single integrated package with optimized internal routing, the patent achieves minimal wire length and contact area for parasitic effects. The standardized integration process maintains ease of manufacture through established semiconductor packaging techniques.
3Productivity
If contact area is maximized to reduce parasitic effects, then switching frequency improves, but device size increases
Solution Approach 1:
The patent uses a nested structure where GaN transistor dies are mounted on an insulating substrate within a compact integrated package. This arrangement maximizes contact area between components and the substrate for reduced parasitic effects and improved switching frequency, while the overall package remains compact through efficient spatial utilization.
Data Source
AI summary
An integrated circuit can include: a bottom structure; at least one GaN transistor die, where each GaN transistor die includes at least one power switching device; a silicon die including a control circuit for controlling the power switching device; and where the GaN transistor die and the silicon die are arranged on the bottom structure, and an electrical connection between the control circuit and the power switching device includes corresponding patterned metal structures arranged in the bottom structure.